ISL6580 Datasheet, PDF (14/31 Pages) Intersil Corporation – Integrated Power Stage

ISL6580
Above the resonant frequency of the output LC filter (10kHz
in this case) the gain falls at a rate of 40dB/decade and the
phase shift approaches –180 degrees. At a frequency
above the F = 1/(2ðC*ESR) = 500kHz in this case) the gain
slope changes to –20dB/decade and the phase shift
approaches –90 degrees.
In a closed loop control system, the output is subtracted from
a reference voltage to produce an error voltage. The error
voltage is amplified and fed to the output stage. In a buck
regulator the output stage consists of a Pulse Width
Modulator (PWM), switching transistors (typically
MOSFETs), series inductor(s) and output capacitors. High
gain feedback reduces variation in the output due to
changes in input voltage, load current and component
values. However, high gain at high frequencies can cause
excessive over shoot in response to transients ( if phase
shift > 120 degrees and gain > 0dB ) or oscillation ( if phase
shift > 180 degrees and gain > 0dB ). The trade off in
designing the loop compensation is to achieve fast response
to transients without excessive overshoot or oscillation.
The ISL6580 subtracts a reference from the output voltage
to produce an error voltage. It converts the error voltage to a
6 bit digital number and sends it to the ISL6590 controller.
The controller processes the error number numerically to
provide gain (Proportional), phase lag (Integration) and
phase lead (Derivative) functions. This forms the digital PID
control.
FIGURE 14. TYPICAL ANALOG ERROR AMPLIFIER AND
COMPENSATION
Adjusting The Digital PID
FIGURE 12. TYPICAL ANALOG VOLTAGE LOOP BLOCK
DIAGRAM
FIGURE 15. DIGITAL PID COMPENSATOR
Frequency response of the digital PID compensator is
determined by the Kp, Ki, Kd factors. These factors are
stored in nonvolatile memory and are loaded in the controller
at power on reset. The system designer sets the PID
compensators frequency response using user interface
software. The designer enters the frequencies of the
desired poles and zeros and user interface software
calculates the Kp, Ki and Kd factors. the software will
calculate and display the frequency response of the
feedback and the closed loop system.
FIGURE 13. DIGITAL CONTROL LOOP BLOCK DIAGRAM
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