ISL6402 Datasheet, PDF (14/19 Pages) Intersil Corporation – 300kHz Dual, 180 Degree Out-of-Phase, Step-Down PWM and Single Linear Controller

ISL6402
Due to the current loop feedback, the modulator has a single
pole response with -20dB slope at a frequency determined
by the load.
F_PO
=
----------------¹----------------
2π ⋅ R_O ⋅ C_O
,
where R_O is load resistance and C_O is load capacitance. For
this type of modulator, a Type 2 compensation circuit is
usually sufficient.
Figure 19 shows a Type 2 amplifier and its response along
with the responses of the current mode modulator and the
converter. The Type 2 amplifier, in addition to the pole at
origin, has a zero-pole pair that causes a flat gain region at
frequencies in between the zero and the pole.
F_Z
=
--------------¹----------------
2π ⋅ R₂ ⋅ C₁
=
6kHz
F_P
=
--------------¹----------------
2π ⋅ R₁ ⋅ C₂
=
600 k H z
CONVERTER
EA
G_M = 17.5dB
MODULATOR
F_PO
C2
R2 ^C1
R1
TYPE 2 EA
G_EA = 18dB
F_Z
F_P
F_C
upper resistor R1 of the divider that sets the output voltage
value. Please refer to the output inductor and capacitor
selection sections for further details.
Linear Regulator
The linear regulator controller is a transconductance
amplifier with a nominal gain of 2 A/V. The N-channel
MOSFET output device can sink a minimum of 50mA. The
reference voltage is 0.8V. With zero volts differential at it’s
input, the controller sinks 21mA of current. An external PNP
transistor or PFET pass element can be used. The dominant
pole for the loop can be placed at the base of the PNP (or
gate of the PFET), as a capacitor from emitter to base
(source to gate of a PFET). Better load transient response is
achieved however, if the dominant pole is placed at the
output, with a capacitor to ground at the output of the
regulator.
Under no-load conditions, leakage currents from the pass
transistors supply the output capacitors, even when the
transistor is off. Generally this is not a problem since the
feedback resistor drains the excess charge. However,
charge may build up on the output capacitor making V_LDO
rise above its set point. Care must be taken to insure that the
feedback resistor’s current exceeds the pass transistors
leakage current over the entire temperature range.
The linear regulator output can be supplied by the output of
one of the PWMs. When using a PFET, the output of the
linear will track the PWM supply after the PWM output rises
to a voltage greater than the threshold of the PFET pass
device. The voltage differential between the PWM and the
linear output will be the load current times the r_DS(ON).
Figure 20 shows the linear regulator (2.5V) startup waveform
and the PWM (3.3V) startup waveform.
FIGURE 19. FEEDBACK LOOP COMPENSATION
The zero frequency, the amplifier high-frequency gain, and
the modulator gain are chosen to satisfy most typical
applications. The crossover frequency will appear at the
point where the modulator attenuation equals the amplifier
high frequency gain. The only task that the system designer
has to complete is to specify the output filter capacitors to
position the load main pole somewhere within one decade
lower than the amplifier zero frequency. With this type of
compensation plenty of phase margin is easily achieved due
to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load pole
is positioned too much to the left side on the frequency axis
due to excessive output filter capacitance. In this case, the
ESR zero placed within the 1.2kHz to 30kHz range gives
some additional phase ‘boost’. Some phase boost can also
be achieved by connecting capacitor C_Z in parallel with the
14
V_OUT2 1V/DIV
V_OUT3 1V/DIV
FIGURE 20. LINEAR REGULATOR STARTUP WAVEFORM
FN9123.3
November 8, 2004