ISL6217A Datasheet, PDF (14/20 Pages) Intersil Corporation – Precision Multi-Phase Buck PWM Controller for Intel, Mobile Voltage Positioning IMVP-IV™ and IMVP-IV+™

ISL6217A
R1
C2
FB
R2 C1
COMP
CDCPL
V _IN
EA+
_
VDROOP _RDROOP
+
SOFT
CSOFT
ERROR
AMPLIFIER
-
+
IDROOP
IMVP-IV_
IMVP-IV+_
REFERENCE
BALANCE
+ ^{Σ VERROR1 +}
-
-
PWM 1
CIRCUIT
COMPARATOR
+
Σ
-
CURRENT
SENSING
IAVERAGE _CURRENT
AVERAGING
-
+
Σ
CURRENT
SENSING
ISL6217A
+ ^{- VERROR2}
Σ
+
BALANCE
-
PWM 2
CIRCUIT
COMPARATOR
UG1
LG1
ISEN1
Q1 L01
Q2
RISEN1
IL1
PHASE
ISEN2
UG2
LG2
RISEN2
+Vrdso-n _VIN
PHASE
Q3
L ₀₂
-
Vrdson ^IL2
Q4 ₊
V _CORE
COUT RLOAD
FIGURE 9. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6217A VOLTAGE AND CURRENT CONTROL LOOPS FOR A TWO CHANNEL
REGULATOR
Battery Feed-Forward Compensation - VBAT
The ISL6217A incorporates Battery Voltage Feed-Forward
Compensation, as shown in Figure 8. This compensation
provides a constant Pulse Width Modulator Gain
independent of battery voltage. An understanding of this
gain is required for proper loop compensation. The Battery
Voltage is connected directly to the ISL6217A by way of the
VBAT pin, and the gain of the system ramp modulator is a
constant 6.0.
Fault Protection
The ISL6217A protects the CPU from damaging stress
levels. The overcurrent trip point is integral in preventing
output shorts of varying degrees from causing current spikes
that would damage a CPU. The output overvoltage and
undervoltage detection features insure a safe window of
operation for the CPU.
Output Voltage Monitoring
VSEN is connected to the local CORE Output Voltage and is
used for PGOOD, undervoltage and overvoltage sensing
only. Refer to the “Block Diagram”.
The voltage on VSEN is compared with two voltage levels
which indicate an overvoltage or undervoltage condition of
the output. Violating either of these conditions results in the
PGOOD pin toggling low to indicate a problem with the
output voltage.
PGOOD
As previously described, the ISL6217A PGOOD pin
operates as both an input and an output. During start-up, the
PGOOD pin operates as an input. Refer to Figure 10.
RST#
EN
SET
SQ
RQ
IPGT
CLR
t
START
~ 100ns
IISSLL66221177A
3.3V
3.3V
START
1.2K
PGOOD
10K
3.3V
10K
ISL6227
PGOOD
V _ccp
PGOOD
Vcc_mch
t
3ms-12ms
CPU-UP# =
UV# and OV#
CLK_ENABLE#
IMVP4_PWRGD
FIGURE 10. INTERNAL PGOOD CIRCUITRY FOR THE
ISL6217A CORE VOLTAGE REGULATOR
As per the IMVP-IV™ and IMVP-IV+™ specification, once
the ISL6217A CORE regulator regulates to the “Boot”
voltage, it waits for the PGOOD logic HIGH signals from the
Vccp and Vcc_mch regulators. The Intersil ISL6227 is a
14
FN9107.3
June 30, 2005