ISL4238E Datasheet, PDF (14/17 Pages) Intersil Corporation – QFN Packaged, ±15kV ESD Protected, +2.7V to +5.5V, 10Nanoamp, 250kbps/1Mbps, RS-232 Transceivers with Enhanced Automatic Power-down

ISL4238E, ISL4244E, ISL4245E
5V/DIV.
T1_IN
T1_OUT
R1_OUT
V_CC = +3.3V
C1 - C4 = 0.1µF
2µs/DIV.
FIGURE 15. ISL4245E LOOPBACK TEST AT 250kbps
5V/DIV.
T1_IN
T1_OUT
R1_OUT
V_CC = +3.3V
C1 - C4 = 0.1µF
0.5µs/DIV.
FIGURE 16. ISL4245E LOOPBACK TEST AT 1Mbps
(C_L = 250pF)
Interconnection with 3V and 5V Logic
The ISL4238E, ISL4244E, ISL4245 directly interface with 5V
CMOS and TTL logic families. Nevertheless, with the
ISL4238E, ISL4244E, ISL4245 at 3.3V, and the logic supply
at 5V, AC, HC, and CD4000 outputs can drive ISL4238E,
ISL4244E, ISL4245 inputs, but ISL4238E, ISL4244E,
ISL4245 outputs do not reach the minimum V_IH for these
logic families. See Table 4 for more information.
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
V_CC
SUPPLY
VOLTAGE
(V)
COMPATIBILITY
3.3
3.3 Compatible with all CMOS families.
5
5
Compatible with all TTL and CMOS
logic families.
5
3.3 Compatible with ACT and HCT
CMOS, and with TTL. ISL4238E,
ISL4244E, ISL4245 outputs are
incompatible with AC, HC, and
CD4000 CMOS inputs.
±15kV ESD Protection
All pins on ISL4238E, ISL4244E, ISL4245 devices include
ESD protection structures, but the RS-232 pins (transmitter
outputs and receiver inputs) incorporate advanced
structures which allow them to survive ESD events up to
±15kV. The RS-232 pins are particularly vulnerable to ESD
damage because they typically connect to an exposed port
on the exterior of the finished product. Simply touching the
port pins, or connecting a cable, can cause an ESD event
that might destroy unprotected ICs. These new ESD
structures protect the device whether or not it is powered up,
protect without allowing any latchup mechanism to activate,
and don’t interfere with RS-232 signals as large as ±25V.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5kΩ current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330Ω limiting resistor. The HBM method
determines an ICs ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to ±15kV.
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge
storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into this
device’s RS-232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board
level protection on the RS-232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. The “E” device RS-232 pins withstand
±15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-232 pins.
14
FN8038.5
May 13, 2010