ISL28110 Datasheet, PDF (14/19 Pages) Intersil Corporation – Precision Low Noise JFET Operational Amplifiers

ISL28110, ISL28210
Applications Information
Functional Description
The ISL28110 and ISL28210 are single and dual 12.5
MHz precision JFET input op amps. These devices are
fabricated in the PR40 Advanced SOI bipolar-JFET
process to ensure latch-free operation. The precision
JFET input stage provides low input offset voltage (300µV
max @ +25°C), low input voltage noise (6nV/√Hz), and
input current noise that is very low with virtually no 1/f
component. A high current complementary NPN/PNP
emitter-follower output stage provides high slew rate and
maintains excellent THD+N performance into heavy
loads (0.0003% @ 10V_P-P @ 1kHz into 600Ω).
Operating Voltage Range
The devices are designed to operate over the 9V (±4.5V)
to 40V (±20V) range and are fully characterized at 10V
(±5V) and 30V (±15V). The JFET input stage maintains
high impedance over a maximum input differential
voltage range of ±33V. Internal ESD protection diodes
clamp the non-inverting and inverting inputs to one diode
drop above and below the V+ and V- the power supply
rails (“Pin Descriptions” on page 2, CIRCUIT 1).
Input ESD Diode Protection
The JFET gate is a reverse-biased diode with >33V
reverse breakdown voltage which enables the device to
function reliably in large signal pulse applications without
the need for anti-parallel clamp diodes required on
MOSFET and most bipolar input stage op amps. No
special input signal restrictions are needed for power
supply operation up to ±15V, and input signal distortion
caused by nonlinear clamps under high slew rate
conditions are avoided. For power supply operation
greater than ±16V (>32V), the internal ESD clamp
diodes alone cannot clamp the maximum input
differential signal to the power supply rails without the
risk of exceeding the 33V breakdown of the JFET gate.
Under these conditions, differential input voltage limiting
is necessary to prevent damage to the JFET input stage.
In applications where one or both amplifier input
terminals are at risk of exposure to voltages beyond the
supply rails, current limiting resistors may be needed at
each input terminal (see Figure 39 R_IN+, R_IN-) to limit
current through the power supply ESD diodes to 20mA.
V+
V_IN-
R_IN-
-
V_IN+
R_IN
+
R_L
V-
FIGURE 39. INPUT ESD DIODE CURRENT LIMITING
JFET Input Stage Performance
The ISL28110, ISL28210 JFET input stage has the linear
gain characteristics of the MOSFET but can operate at
high frequency with much lower noise. The reversed-
biased gate PN gate junction has significantly lower gate
capacitance enabling input slew rates that rival op amps
using bipolar input stages. The added advantage for
high impedance, precision amplifiers is the lack of a
significant 1/f component of current noise (Figures 11,
12) as there is virtually no gate current.
The input stage JFETs are bootstrapped to maintain a
constant JFET drain to source voltage which keeps the
JFET gate currents and input stage frequency response
nearly constant over the common mode input range of
the device. These enhancements provide excellent
CMRR, AC performance and very low input distortion
over a wide temperature range. The common mode
input performance for offset voltage and bias current is
shown in FIGURE 40. Note that the input bias current
remains low even after the maximum input stage
common mode voltage is exceeded (as indicated by the
abrupt change in input offset voltage).
10
500
8
V_S = ±15V
INPUT OFFSET VOLTAGE (V_OS) _{T = +25°C}
400
6
300
4
200
2
100
0
0
-2
-100
-4
-200
-6
INPUT BIAS (I_B)
-8
-300
-400
-10
-15
-10
-5
0
5
V_CM (V)
-500
10
15
FIGURE 40. INPUT OFFSET VOLTAGE AND BIAS
CURRENT vs COMMON MODE INPUT
VOLTAGE
Output Drive Capability
The complementary bipolar emitter follower output
stage features low output impedance (Figure 40) and is
capable of substantial current drive over the full
temperature range (Figures 25, 26) while driving the
output voltage close to the supply rails. The output
current is internally limited to approximately ±50mA at
+25°C. The amplifiers can withstand a short circuit to
either rail as long as the power dissipation limits are not
exceeded. This applies to only 1 amplifier at a time for
the dual op amp. Continuous operation under these
conditions may degrade long term reliability.
Output Phase Reversal
Output phase reversal is a change of polarity in the
amplifier transfer function when the input voltage
exceeds the supply voltage. The ISL28110 and ISL28210
are immune to output phase reversal, out to 0.5V
beyond the rail (V_ABS MAX) limit. Beyond these limits,
the device is still immune to reversal to 1V beyond the
14
FN6639.0
September 13, 2010