ISL267450 Datasheet, PDF (14/19 Pages) Intersil Corporation – 12-Bit, 1MSPS SAR ADCs

ISL267450
FIGURE 27. NORMAL MODE OPERATION
CONVERTER OPERATION
The ISL267450 is designed to minimize power consumption by
only powering up the SAR comparator during conversion time.
When the converter is in track mode (its sample capacitors are
tracking the input signal), the SAR comparator is powered down.
The state of the converter is dictated by the logic state of CS.
When CS is high, the SAR comparator is powered down while the
sampling capacitor array is tracking the input. When CS
transitions low, the capacitor array immediately captures the
analog signal that is being tracked. After CS is taken low, the
SCLK pin is toggled 16 times. For the first 3 clocks, the
comparator is powered up and auto-zeroed, then the SAR
decision process is begun. This process uses 12 SCLK cycles.
Each SAR decision is presented to the SDATA output on the next
clock cycle after the SAR decision is performed. The SAR process
(12 bits) is completed on SCLK cycle 15. At this point in time, the
SAR comparator is powered down and the capacitor array is
placed back into Track mode. The last SAR comparator decision
is output from SDATA on the 16th SCLK cycle. When the last data
bit is output from SDATA, the output switches to a logic 0 until CS
is taken high, at which time, the SDATA output enters a High-Z
state.
Figure 27 illustrates the serial port system timing for the
ISL267450.
POWER-ON RESET
When power is first applied, the ISL267450 performs a power-on
reset that requires approximately 2.5ms to execute. After this is
complete, a single dummy conversion must be executed (by
taking CS low) in order to initialize the switched capacitor track
and hold. The dummy conversion cycle will take 889ns with an
18MHz SCLK. Once the dummy cycle is complete, the ADC mode
will be determined by the state of CS. Regular conversions can be
started immediately after this dummy cycle is completed and
time has been allowed for proper acquisition.
ACQUISITION TIME
To achieve the maximum sample rate (1MSps) in the ISL267450
device, the maximum acquisition time is 200ns. For slower
conversion rates, or for conversions performed using a slower
SCLK value than 18MHz, the minimum acquisition time is 200ns.
This minimum acquisition time also applies to the device when
operated at 3V supply or if short cycling is utilized.
SHORT CYCLING
In cases where a lower resolution conversion is acceptable, CS
can be pulled high before all 12 bits are clocked out. This is
referred to as short cycling, and it can be used to further optimize
power dissipation. In this mode, a lower resolution result will be
output, but the ADC will enter static mode sooner and exhibit a
lower average power consumption than if the complete
conversion cycle were carried out. The minimum acquisition time
(tACQ) requirement of 200ns must be met for the next
conversion to be valid.
POWER vs THROUGHPUT RATE
The ISL267450 provides reduced power consumption at lower
conversion rates by automatically switching into a low-power
mode after completing a conversion. The average power
consumption of the ADC decreases at lower throughput rates.
Figure 28 shows the typical power consumption over a wide
range of throughput rates.
100
10
V_DD = 5V
1
0.1
V_DD = 3V
0.01
0
50
100 150 200 250 300 350
THROUGHPUT (kSPS)
FIGURE 28. POWER CONSUMPTION vs THROUGHPUT RATE
14
FN8341.0
August 10, 2012