ISL26102_14 Datasheet, PDF (14/21 Pages) Intersil Corporation – Low-Noise 24-bit Delta Sigma ADC

ISL26102, ISL26104
logic 0 to indicate that data is to be read from an on-chip register.
The remaining seven bits of the address byte contains the
address of the register that is to be read. To begin the read cycle,
CS must first be taken low with SCLK low and be low for at least
125ns before SCLK is taken high to latch the first data bit. The
eight address bits will be latched into the port by rising edges of
SCLK. The data set-up time (t_ds) of the data bits to the rising edge
of SCLK is 50ns (one half clock cycle of the highest SCLK rate is
1/(2*4MHz) = 125ns). Data hold time (t_dh) is also 50ns. Address
bits should be advanced to the next bit on falling edges of SCLK.
Once the address byte has been written, the port will output a
byte from the selected 8-bit register onto the SDO pin. A total of
16 SCLKs are required to write the address byte and then read
the 8-bit register output. The timing for reading from on-chip
registers is illustrated in Figure 12.
Reading Conversion Data
Reading conversion data is done in a different manner than
when reading on-chip registers. After writing into the Conversion
Control register to instruct the A/D to start conversions, the user
will then wait for the SDO/RDY signal to fall. Once the SDO/RDY
signal falls, the 24-bit conversion data word becomes available to
the port. To read the conversion word, the CS signal should be left
in the logic 1 state and 24 SCLKs issued to the SCLK pin. The first
rising SCLK edge will make the MSB data bit of the 24-bit word
become available. The falling edge of the first SCLK will latch the
bit into the external receiving logic device. Subsequent rising
edges of SCLK will cause the port output to advance to the next
data bit. Once the last data bit is read, the SCLK signal should
remain low until another conversion word is available or until a
command to write or read an on-chip register is performed.
SDO/RDY goes low to signal that a conversion has been
performed and that the conversion word is available. If the
analog input signal goes over range this may cause the
modulator to become unstable. If this condition occurs the
modulator resets itself. The output code will be held at full scale
but the effect of the modulator being reset will cause the
SDO/RDY signal to fall at only one fourth of its word rate. This
occurs because when the modulator is reset, the digital filter is
also reset and it takes four conversion periods for the filter to
accumulate enough modulator bit stream information to produce
an accurate conversion result.
CS
t_cs
t_sc
SCLK
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
0
1
2
3
4
5
6
t_ds t_dh
SDI
W
A
AA
A
A
A
AD
D
D
D
D
D
D
D
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DON’T CARE
DON’T CARE
FIGURE 11. WRITE ON-CHIP REGISTER WAVEFORMS
CS
t_cs
t_sc
SCLK
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
0
1
2
3
4
5
6
t_ds t_dh
DON’T CARE
SDI
X
X
R
A
A
A
6
5
4
AA
A
A
X
X
3
2
1
0
X
X
XX
X
XX
X
X
XX
X
XX
X
X
SDO
XX (DON’T CARE)
Q
Q
Q
Q
Q
QQ
QX
7
6
5
4
3
2
1
0
X
FIGURE 12. READ ON-CHIP REGISTER WAVEFORMS
CS
DATA READY
DATA
SDO/RDY
MSB
222
321
SCLK
1234
LSB
0
2
4
NEW DATA READY
FIGURE 13. READING CONVERSION DATA WORD WAVEFORMS
14
FN7608.0
October 12, 2012