HSP43124_07 Datasheet, PDF (14/18 Pages) Intersil Corporation – Serial I/O Filter

HSP43124
FCLK/SCLK Uncertainty Region
Figure 13 shows a clocking relationship for the HSP43124
Serial I/O filter that could result in an uncertainty at the
output. For simplicity, the frequency of FCLK and SCLK are
assumed to be equal to each other, and CLKOUT is
assumed to be equal to FLCK. When the rising edge of
FCLK lags behind the rising edge of SCLK by a small
amount of time (T_SCFC), then the FCLK edge on which
samples are read into the filter compute engine is
determined by a race condition. In order to insure proper
function for the HSP43124, T_SCFC must be greater than
3.8ns.
If exact timing (a particular clock edge for a specific data bit)
then make SCLK and FCLK synchronous. If FCLK and
SCLK are asynchronous, there will be jitter (a specific data
bit will be output as 1 of 2 possible clock edges depending
on the FCLK to SCLK phasing). For multiple part
applications, use synchronous clocks or use separate syncs
on what receives each data, as the outputs may vary by a
clock cycle.
SCLK
SYNCIN
DIN MSB
LSB
MSB
FCLK
SYNCOUT
DOUT
T_SCFC
MSB
LSB
MSB
FIGURE 13. FCLK/SCLK UNCERTAINTY REGION
Asynchronous FCLK and SCLK
If FCLK and SCLK are asynchronous clocks, then the output
sample rate (tracked by SYNCOUT) of the HSP43124 might
jitter in a real time system. This jitter will be demonstrated
using an SCLK with a period that is 3/2 times the period of
FCLK (i.e., F_FCLK/F_SCLK = 3/2), as shown in Figure 14A
and Figure 14B. If the LSB occurs when there are two FCLK
edges in one SCLK period (see Figure 14A), then a null data
bit will occur in the DOUT data stream. If the LSB occurs
when there is one FCLK edge in one SCLK period for the
LSB (see Figure 14B), then no null data bit will occur. Given
the 3/2 period relationship between FCLK and SCLK, the
user can see that the SYNCOUT jitters by one clock. For
example, if the output data is represent by 16 bits, then the
number of CLKOUT rising edges between SYNCOUT pulses
should jitter between 15 and 16.
The SYNCOUT jitter demonstrated by the 3/2 frequency
example can be generalized to other asynchronous
F_FCLK/F_SCLK ratios. Setting the frequencies for FCLK and
SCLK at integer multiples of one another eliminates timing
jitter in the output sample rate.
SCLK
1
2
SYNCIN
DIN MSB
LSB
MSB
CLKOUT
SYNCOUT
1
2
DOUT MSB
LSB NULL MSB
FIGURE 14A. NUMBER OF CLKOUT = NUMBER OF BITS + 1
FOR THE TIME PERIOD BETWEEN SYNCOUTS
WHERE F_FCLK/F_SCLK = 3/2
SCLK
1
2
SYNCIN
DIN
MSB
LSB
MSB
CLKOUT
1
2
SYNCOUT
DOUT
MSB
LSB MSB
FIGURE 14B. NUMBER OF CLKOUT = NUMBER OF BITS FOR
THE TIME PERIOD BETWEEN SYNCOUTS
WHERE F_FCLK/F_SCLK = 3/2
14