HI5703 Datasheet, PDF (14/18 Pages) Intersil Corporation – 10-Bit, 40 MSPS A/D Converter

The single ended analog input can be DC coupled
(Figure 19) as long as the input is within the analog input
common mode voltage range.
V_IN
VDC
V_IN+
R
C
HI5703
VDC
V_IN-
FIGURE 19. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 19 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from V_IN+ to V_IN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before
driving the HI5703. Refer to the application notes AN9534,
“Using the HI5703 Evaluation Board”, and AN9413, “Driving
the Analog Input of the HI5702”. Application note AN9413
applies to the HI5703 as well as the HI5702 and describes
several different ways of driving the analog differential
inputs.
Digital Output Control and Clock Requirements
The HI5703 provides a standard high-speed interface to
external TTL logic families.
In order to ensure rated performance of the HI5703, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL levels.
Performance of the HI5703 will only be guaranteed at
conversion rates above 1 MSPS. This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1 MSPS will have to be
performed before valid data is available.
A Data Format Select (DFS) pin is provided which will
determine the format of the digital data outputs. When at
logic low, the data will be output in offset binary format.
When at logic high, the data will be output in two’s
complement format. Refer to Table 2 for further information.
The output enable pin, OE, when pulled high will three-state
the digital outputs to a high impedance state. Set the OE
input to logic low for normal operation.
OE INPUT
DIGITAL DATA OUTPUTS
0
Active
1
High Impedance
Supply and Ground Considerations
The HI5703 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The digital data outputs also have a separate supply
pin, DV_CC2, which can be powered from a 3.3V to 5.0V
supply. This allows the outputs to interface with 3.3V logic if
so desired.
The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the HI5703 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply and ground pins should be
isolated by ferrite beads from the digital supply and ground
pins.
Refer to the application notes “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
Static Performance Definitions
Offset Error (V_OS)
The midscale code transition should occur at a level ¹/₄ LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input that
is ³/₄ LSB below positive Fullscale (+FS) with the offset error
removed. Full-scale error is defined as the deviation of the
actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and full scale error (in LSBs) is
noted.
4-14