HC5526_03 Datasheet, PDF (14/20 Pages) Intersil Corporation – ITU CO/PABX SLIC with Low Power Standby

HC5526
process of ring trip is initiated when the logic input pins are in the
following states: E0 = 0, E1 = 1/0, C1 = 1 and C2 = 0. This logic
condition connects the ring trip comparator to the DET output,
and causes the Ringrly pin to energize the ring relay. The ring
relay connects the tip and ring of the phone to the external
circuitry in Figure 19. When the phone is on-hook the DT pin is
+_-
TIP
R₁
RING
CASE 1
I_METALLIC
←
CASE 2
CASE 3
I_LONGITUDINAL
←
I_LONGITUDINAL
→
R₂
-
+
HC5526
more positive than the DR pin and the DET output is high. For
off-hook conditions DR is more positive than DT and DET goes
low. When DET goes low, indicating that the phone has gone
off-hook, the SLIC is commanded by the logic inputs to go into
the active state. In the active state, tip and ring are once again
connected to the phone and normal operation ensues.
gm₁(I_METALLIC)
CURRENT
LOOP
COMPARATOR
gm₁
gm₂(I_TIP - I_RING)
gm₂
I_GK
R_H
+_-
GROUND
KEY
D₂
D₁
I₁
COMPARATOR
R_D
R_H
I_{RD RD}
C_D
+_-
-
V_REF
1.25V
V_EE
-5V
DIGITAL MULTIPLEXER
DET
FIGURE 18. LOOP CURRENT AND GROUND KEY DETECTORS
Figure 19 illustrates battery backed unbalanced ring injected
ringing. For tip injected ringing just reverse the leads to the
phone. The ringing source could also be balanced.
NOTE: The DET output will toggle at 20Hz because the DT input is
not completely filtered by C_RT. Software can examine the duty cycle
and determine if the DET pin is low for more that half the time, if so
the off-hook condition is indicated.
R_RT
R₃^CRT
R₄
TIP _ERG
R_{1 DT}
-
+
DR
R₂
RING TRIP
COMPARATOR
DET
RING
RING
RELAY
V_BAT
RINGRLY
HC5526
FIGURE 19. RING TRIP CIRCUIT FOR BATTERY BACKED RINGING
Longitudinal Impedance
The feedback loop described in Figure 20(A, B) realizes the
desired longitudinal impedances from tip to ground and from
ring to ground. Nominal longitudinal impedance is resistive
and in the order of 22Ω.
In the presence of longitudinal currents this circuit attenuates
the voltages that would otherwise appear at the tip and ring
terminals, to levels well within the common mode range of
the SLIC. In fact, longitudinal currents may exceed the
programmed DC loop current without disturbing the SLIC’s
VF transmission capabilities.
The function of this circuit is to maintain the tip and ring
voltages symmetrically around V_BAT/2, in the presence of
longitudinal currents. The differential transconductance
amplifiers G_T and G_R accomplish this by sourcing or sinking
the required current to maintain V_C at V_BAT/2.
When a longitudinal current is injected onto the tip and ring
inputs, the voltage at V_C moves from it’s equilibrium value
V_BAT/2. When V_C changes by the amount ∆V_C, this change
appears between the input terminals of the differential
transconductance amplifiers G_T and G_R. The output of G_T
and G_R are the differential currents ∆I₁ and ∆I₂, which in
turn feed the differential inputs of current sources I_T and I_R
respectively. I_T and I_R have current gains of 250 single
ended and 500 differentially, thus leading to a change in I_T
and I_R that is equal to 500(∆_I) and 500(∆I₂).
The circuit shown in Figure 20(B) illustrates the tip side of
the longitudinal network. The advantages of a differential
input current source are: improved noise since the noise due
to current source 2I_O is now correlated, power savings due
to differential current gain and minimized offset error at the
Operational Amplifier inputs via the two 5kΩ resistors.
Digital Logic Inputs
Table 1 is the logic truth table for the TTL compatible logic
input pins. The HC5526 has two enable inputs pins (E0, E1)
and two control inputs pins (C1, C2).
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