ZL6105 Datasheet, PDF (13/35 Pages) Intersil Corporation – Digital DC/DC Controller with Drivers and Auto

ZL6105
The output voltage can be determined from the R₀ (Index0) and
R₁ (Index1) values using Equation 4:
V_OUT
=
Index0 + (25 ×
100
Index1)
(EQ. 4)
Single Resistor Output Voltage Setting Mode
Some applications desire the output voltage to be set using a
single resistor. This can be accomplished using a resistor on the
V1 pin while the V0 pin is tied to SGND. Table 4 lists the available
output voltage settings with a single resistor.
SMBus Mode
The output voltage may be set to any value between 0.6V and
5.0V using a PMBus command over the I²C/SMBus interface.
See Application Note AN2033 for details.
Start-up Procedure
The ZL6105 follows a specific internal start-up procedure after
power is applied to the VDD pin. Table 5 describes the start-up
sequence.
TABLE 4. SINGLE RESISTOR V_OUT SETTING
R_V1
(kΩ)
R_V0
V_OUT
10
LOW
0.60
11
LOW
0.65
12.1
LOW
0.70
13.3
LOW
0.75
14.7
LOW
0.80
16.2
LOW
0.85
17.8
LOW
0.90
19.6
LOW
0.95
21.5
LOW
1.00
23.7
LOW
1.05
26.1
LOW
1.10
28.7
LOW
1.15
31.6
LOW
1.20
34.8
LOW
1.25
38.3
LOW
1.30
42.2
LOW
1.40
46.4
LOW
1.50
51.1
LOW
1.60
56.2
LOW
1.70
61.9
LOW
1.80
68.1
LOW
1.90
75
LOW
2.00
82.5
LOW
2.10
90.9
LOW
2.20
100
LOW
2.30
110
LOW
2.50
121
LOW
3.00
TABLE 4. SINGLE RESISTOR V_OUT SETTING (Continued)
R_V1
(kΩ)
R_V0
V_OUT
133
LOW
3.30
147
LOW
4.00
162
LOW
5.00
178
LOW
5.50
VIN
GH
ZL
SW
GL
V0 V1
R0
21. 5 kΩ
R1
16.2 kΩ
V_OUT
1.33V
FIGURE 9. OUTPUT VOLTAGE RESISTOR SETTING EXAMPLE
If the device is to be synchronized to an external clock source, the
clock frequency must be stable prior to asserting the EN pin. The
device requires approximately 5ms to 10ms to check for specific
values stored in its internal memory. If the user has stored values
in memory, those values will be loaded. The device will then
check the status of all multi-mode pins and load the values
associated with the pin settings.
Once this process is completed, the device is ready to accept
commands via the I²C/SMBus interface and the device is ready
to be enabled. Once enabled, the device requires a minimum
delay period following an enable signal and prior to ramping its
output, as described in “Soft-Start Delay and Ramp Times” on
page 14. If a soft-start delay period less than the minimum has
been configured (using PMBus commands), the device will
default to the minimum delay period. If a delay period greater
than the minimum is configured, the device will wait for the
configured delay period prior to starting to ramp its output.
After the delay period has expired, the output will begin to ramp
towards its target voltage according to the pre-configured soft-
start ramp time that has been set using the SS pin. It should be
noted that if the EN pin is tied to VDD, the device will still require
approximately 5ms to 10ms before the output can begin its
ramp-up as described in Table 5.
13
FN6906.3
February 8, 2011