X9258_14 Datasheet, PDF (13/19 Pages) Intersil Corporation – Quad Digital Controlled Potentiometers

X9258
Power-Up and Power-Down Requirement
The are no restrictions on the sequencing of the bias supplies
V_CC, V+, and V- provided that all three supplies reach their final
values within 1ms of each other. At all times, the voltages on
the potentiometer pins must be less than V+ and more than V-.
The recall of the wiper position from nonvolatile memory is not
in effect until all supplies reach their final value. The V_CC ramp
rate specification is always in effect.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Level
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC x 0.5
Equivalent AC Load Circuit
5V
1533Ω
SDA OUTPUT
100pF
2.7V
100pF
Test Circuit #3 SPICE Macro Model
MACRO MODEL
R_TOTAL
R_H
R_L
C_L
C_H
C_W
10pF
10pF
25pF
R_W
AC Timing
Over recommended operating conditions, unless otherwise specified.
SYMBOL
PARAMETER
MIN
MAX
(Note 12) (Note 12)
UNIT
f_SCL
Clock Frequency
400
kHz
t_CYC
Clock Cycle Time
2500
ns
t_HIGH
Clock High Time
600
ns
t_LOW
Clock Low Time
1300
ns
t_SU:STA
Start Setup Time
600
ns
t_HD:STA
Start Hold Time
600
ns
t_SU:STO
Stop Setup Time
600
ns
t_SU:DAT
SDA Data Input Setup Time
100
ns
t_HD:DAT
SDA Data Input Hold Time
30
ns
t_R
SCL and SDA Rise Time (Note 20)
300
ns
t_F
SCL and SDA Fall Time (Note 20)
300
ns
t_AA
SCL Low to SDA Data Output Valid Time
900
ns
t_DH
SDA Data Output Hold Time
50
ns
T_I
Noise Suppression Time Constant at SCL and SDA Inputs
50
ns
t_BUF
Bus Free Time (Prior to any Transmission)
1300
ns
t_SU:WPA
WP, A0, A1, A2 and A3 Setup Time
0
ns
t_HD:WPA
WP, A0, A1, A2 and A3 Hold Time
0
ns
NOTE:
20. A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
13
FN8168.6
December 15, 2011