X40626 Datasheet, PDF (13/22 Pages) Xicor Inc. – Dual Voltage CPU Supervisor with 64K Serial EEPROM

X40626
Figure 14. Sequential Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
Slave
Address
A
A
A
C
C
C
K
K
K
t
o
p
S₁ S₀ 1
A
C
Data
K
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
X40626 Addressing
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several
parts:
– a device type identifier that is ‘1010’ to access the
array
– one bit of ‘0’.
– next two bits are the device address. (S1 and S0)
– one bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 15.
– After loading the entire Slave Address Byte from the
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is 00H on a power-up condition.
The master must supply the two word address byte as
shown in Figure 15.
13
FN8119.0
March 28, 2005