ISL97649AR5566_15 Datasheet, PDF (13/21 Pages) Intersil Corporation – TFT-LCD Supply + DCP + VCOM Amplifier + Gate Pulse Modulator + RESET

VIN
UVLO
THRESHOLD
0
VGH
RESET
ISL97649AR5566
VDPM
1.215V
VFLK
VGHM
VGH
GPM_LO
SlLoOpPeEisIScontrolled
FVTAOGLHV^VVLMGS^GGHIHT^{HSOW_FwMHUOhEVReiNLCsn}OEV^fRoDIANrEcN^SeD^{Ed Tto}
VGH^g>^o3^eV^{s to low AND}
b^Cy^OR^NTE^{ROLLED BY RE}
VGH>3V
PO^PW^owER^er-O^oNⁿ D^deE^lL^aA^yY^tiT^mIM^eE
D_DEe_Lla_Ay_Yti_Tm_IMe_Eis_IScontrolled
CO^isN^cT^oRⁿO^trL^oL^lE^leD^d
C_DPM
B^bY^y
C_DPM
bCyOCNTEROLLED BY CE
FIGURE 16. GATE PULSE MODULATOR TIMING DIAGRAM
Gate Pulse Modulator Circuit
The gate pulse modulator circuit functions as a three way
multiplexer, switching VGHM between ground, GPM_LO and VGH.
Voltage selection is provided by digital inputs VDPM (enable) and
VFLK (control). HIGH to LOW delay and slew control is provided by
external components on pins CE and RE, respectively.
When VDPM is LOW, the block is disabled and VGHM is
grounded. When the input voltage exceeds UVLO threshold,
VDPM starts to drive an external capacitor. Once VDPM exceeds
1.215V, the GPM circuit is enabled and the output VGHM is
determined by VFLK, RESET signal and VGH voltage. If RESET
signal is high and VFLK is high, VGHM is pulled to VGH. When
VFLK goes low, there is a delay controlled by capacitor CE,
following which, VGHM is driven to GPM_LO, with a slew rate
controlled by resistor RE. Note that GPM_LO is used only as a
reference voltage for an amplifier, and thus does not have to
source or sink a significant DC current.
LOW to HIGH transition is determined primarily by the switch
resistance and the external capacitive load. HIGH to LOW
transition is more complex. Take the case where the block is
already enabled (VDPM is H). When VFLK is H, if CE is not
externally pulled above threshold voltage 1, pin CE is pulled low.
On the falling edge of VFLK, a current is passed into pin CE to
charge the external capacitor up to threshold voltage 2, providing
a delay which is adjustable by varying the capacitor on CE. Once
this threshold is reached, the output starts to be pulled down
from VGH to GPM_LO. The maximum slew current is equal to
500/(RE + 40k), and the dv/dt slew rate is Isl/C_LOAD, where
C_LOAD is the load capacitance applied to VGHM. The slew rate
reduces as VGHM approaches GPM_LO.
If CE is always pulled up to a voltage above threshold 1, zero
delay mode is selected; thus, there will be no delay from FLK
falling to the point where VGHM starts to fall. Slew down currents
will be identical to the previous case.
At power-down, when VIN falls to UVLO, VGHM will be tied to VGH
until the VGH voltage falls to 3V. Once the VGH voltage falls below
3V, VGHM will not be actively driven until VIN is driven. Figure 16
shows the VGHM voltage based on V_IN, VGH and RESET.
VGH/VGL Charge Pump
To provide VGH and VGL rails for the application, two external
charge pumps driven by AVDD and the boost switching node can
be used to generate the desired VGH and VGL, as shown in the
“Application Diagram” on page 3.
The number of charge pump stages can be calculated using
Equations 9 and 10.
VGL_headroom = N^AVDD – 2^N^Vd – VGL  0
(EQ. 9)
VGH_headroom = N + 1AVDD – 2^N^Vd – VGH  0 ^{(EQ. 10)}
Where N is the number of charge pump stages and Vd is the
forward voltage drop of one Schottky diode used in the charge
pump. Vd varies with forward current and ambient temperature,
so it should be the maximum value in the diode datasheet
according to max forward current and lowest temperature in the
application condition.
Once the number of the charge pump stages is determined, the
maximum current that the charge pump can deliver can be
calculated using Equations 11 and 12:
VGL = N^–AVDD + 2^Vd + I_VGL  Freq^C_fly
(EQ. 11)
VGH = AVDD + N^AVDD – 2^Vd – I_VGH  Freq^C_fly (EQ. 12)
Where Freq is the switching frequency of the AVDD boost, C_fly is
the flying capacitance (C₈, C₁₀, C₁₁ in the application diagram).
I_VGL and I_VGH are the loadings of VGL and VGH. The relationships
between minimum flying capacitance and VGL and VGH loadings
are shown in Figures 17 and 18. The flying capacitance must be
higher than the minimum value shown in Figures 17 and 18 for a
certain loading on VGL and VGH.
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September 11, 2015