ISL6295CVZ Datasheet, PDF (13/25 Pages) Intersil Corporation – Low Voltage Fuel Gauge

ISL6295
7
10
S
SMBus Address 0 A
76
43 2 1 0
BT X Bank AH A
7
0
Address Low
A
7
0
# of Bytes (only if BT = 1) _A
7
10
RS
SMBus Address 1 A
7
0
(Additional data bytes if BT =1)
7
0
Last Read Data Byte A/A
7
0
PEC (optional)
A
P
Master controls SDA
Legend:
ISL6295 controls SDA
S
P
RS
A
A
BT
Bank
- Start
- Stop
- Repeated start
- Acknowdedge
- Negative Acknowledge (terminates transaction)
- Block mode indicator bit
- Controls selection of bank:
00: EEPROM
01: RAM / Registers
10: Test Mode Registers
11: Reserved
PEC
- Packet Error Code
AH
Address low
- High order address bits (2)
- Low order address bits (8)
FIGURE 8. ISL6295 SMBus READ TRANSACTION
Memory/Operational Register Description
Memory/Register Map
The ISL6295 internal structure is accessible on a strict
memory mapped basis. The only action directly taken by the
ISL6295 in response to an SMBus command is to read or
write registers, SRAM, or EEPROM locations. Any actions
taken by ISL6295 happen as a result of values written to
internal control registers.
Addressing in ISL6295 consists of 10 bits plus two bank
select bits. Therefore, there are a total of 4K byte locations
that are addressable within the ISL6295, organized as 4
banks of 1024 locations each. Bank 0 is dedicated for the
EEPROM. Bank 1 contains the general-purpose SRAM and
the data, status and control registers. Bank 2 contains test
registers, and Bank 3 is reserved.
Table 1 describes the ISL6295 memory map. The notation is
y:0xzzz where y is the bank number and zzz is the register
address in HEX.
EEPROM
The 256 byte EEPROM is located in bank 0 and occupies
address 0:0x000 to 0:0x0FF. The EEPROM can be read
using Byte or Block transfer modes, but can only be written a
byte at a time. Writing the EEPROM takes approximately
4ms/byte. An EEPROM write cycle command from the
SMBus is immediately acknowledged by the ISL6295 if no
other EEPROM write cycles are in progress. If an EEPROM
read or write cycle is attempted while a previous request to
write is in progress, a negative Acknowledge will be returned
until the previous write cycle is completed.
A read or write to a register or SRAM location will not be
affected by an EEPROM write cycle in progress.
13
FN9074.2
February 8, 2011