ISL6174 Datasheet, PDF (13/16 Pages) Intersil Corporation – Dual Low Voltage Circuit Breaker

GATE
TCB
Iin
ISL6174
GATE
TCB
Iin
FIGURE 21. WOC CIRCUIT BREAKER OPERATION ZOOM
Figure 22 illustrates the GATE response time to an output
short. The time from the input current > 2.2A (I_CB) to the
FET gate being pulled down is ~0.6µs.
GATE
Iin
FIGURE 23. TRANSIENT TO 3.9A OC CIRCUIT BREAKER
OPERATION with TCB OPEN
Dual Voltage Tracking During Turn-on
The ISL6174 Dual Circuit Breaker is also designed to
provide either concurrent or ratiometric tracking of the two
output voltages during turn-on. This capability is critical in
providing power to many high value loads.
The two channels can be forced to track each other by
simply tying their SS pins together and using a common SS
capacitor, C_SS. In addition, their EN pins also must be tied
together. Typical Start-up waveforms in this mode are shown
in Figure 24, where the common C_SS value is 0.066µF.
V_O1
FIGURE 22. SHORTED OUTPUT GATE RESPONSE
The previous scope shots illustrate the performance with a
~18ms circuit breaker delay, t_CB as determined by the
10.5µF cap on TCB pin. Figure 23 shows the performance
with an open TCB pin for the same amplitude of OC event as
shown in Figure 19. Once again, see the TCB pin ramp
duration and t_CB of ~3µs, the intrinsic delay of the IC OC
response.
13
V_O2
FIGURE 24. CONCURRENT TRACKING MODE
If one channel experiences a CB event and turns off, the
other one will too.
To achieve ratiometric tracking, the ratio of the two C_SS must
match the ratio of the two voltages being handled. In the
illustrated case in Figure 25, the 1.5V to 3.3V ratio of 1:2.2 is
FN6830.0
December 19, 2008