ISL6173 Datasheet, PDF(13/20 Page) Intersil Corporation – Dual Low Voltage Hot Swap Controller

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ISL6173 Datasheet, PDF (13/20 Pages) Intersil Corporation – Dual Low Voltage Hot Swap Controller

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ISL6173

Applications Information

Selection of External Components

The typical application circuit of Figure 2 has been used for

this section, which provides guidelines to select the external

component values.

MOSFET (Q1)

This component should be selected on the basis of its

rDS(ON) specification at the expected Vgs (gate to source

voltage) and the effective input gate capacitance (Ciss). One

needs to ensure that the combined voltage drop across the

Rsense and rDS(ON) at the desired maximum current

(including transients) will still keep the output voltage above

the minimum required level. Power dissipation in the device

under short circuit condition should also be an important

consideration especially in auto-retry mode (RTR/LTCH pin

pulled low). Using ISL6173 in latched off mode results in

lower power dissipation in the MOSFET.

Ciss of the MOSFET influences the overcurrent response

time. It is recommended that a MOSFET with Ciss of less

than 10nF be chosen. Ciss will also have an impact on the

SS cap value selection as seen later.

Current Sense Resistor (RSNS)

The voltage drop across this resistor, which represents the

load current (Io), is compared against the set threshold of

the current regulation amplifier. The value of this resistor is

determined by how much combined voltage drop is tolerable

between the source and the load. It is recommended that at

least 20mV drop be allowed across this resistor at max load

current. This resistor is expected to carry maximum full load

current indefinitely. Hence, the power rating of this resistor

must be greater than IO(MAX)2*RSNS.

This resistor is typically a low value resistor and hence the

voltage signal appearing across it is also small. In order to

maintain high current sense accuracy, current sense trace

routing is critical. It is recommended that either a four wire

resistor or the following routing method be used:

LOAD CURRENT CARRYING

TRACES

CURRENT

SENSE

TRACES

RSNS

FIGURE 17. RECOMMENDED CURRENT SENSE RESISTOR

PCB LAYOUT

Current Set Resistor (RSET)

This resistor directly sets the threshold for the current

regulation amplifier and indirectly sets the same for the OC

and WOC comparators in conjunction with RSNS. Once

RSNS has been selected, use Equation 1 (on page 9) to

calculate RSET. Use 20ÂµA for ISET in a typical application.

Reference Current Set Resistor (RREF)

This resistor sets up the current in the internal current

source, IREF/4, shown in Figure 2 for the comparators. The

voltage at the OCREF pin is the same as the internal

bandgap reference. The current (IREF) flowing through this

resistor is simply:

IREF = 1.178/RREF

This current, IREF, should be set at 80ÂµA to force 20ÂµA in the

internal current source as shown in Figure 2, because of the

4:1 current mirror. This equates to the resistor value of

14.7K.

Selection of Rs1 and Rs2

These resistors set the UV detect point. The UV comparator

detects the undervoltage condition when it sees the voltage

at UV pin drop below 0.633V. The resistor divider values

should be selected accordingly.

Charge Pump Capacitor Selection (CP and CV)

CP is the âflying capâ and CV is the smoothing cap of the

charge pump, which operates at 450kHz set internally. The

output resistance of the charge pump, which affects the

regulation, is dependent on the CP value and its ESR,

charge-pump switch resistance, and the frequency and ESR

of the smoothing cap, CV.

It is recommended that CP be kept within 0.022ÂµF

(minimum) to 0.1ÂµF (maximum) range. Only ceramic

capacitors are recommended. Use 0.1ÂµF cap if CPVDD

output is expected to power an external circuit, in which case

the current draw from CPVDD must be kept below 10mA.

CV should at least be 0.47ÂµF (ceramic only). Higher values

may be used if low ripple performance is desired.

Time-out Capacitor Selection (CT)

This capacitor controls the current regulation time-out

period. As shown in Figure 2, when the voltage across this

capacitor exceeds 1.178V, the time-out comparator detects it

and pulls down the gate voltage thus shutting down the

channel. An internal 10ÂµA current source charges this

capacitor. Hence, the value of this capacitor is determined by

the following equation:

CT = (10ÂµA * TOUT)/1.178

Where,

TOUT = Desired time-out period.

FN9186.2

February 15, 2005

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