ISL59483_07 Datasheet, PDF (13/17 Pages) Intersil Corporation – Dual, 500MHz Triple, Multiplexing Amplifiers

ISL59483
Pin Equivalent Circuits
V+
IN
V-
V1+
GNDA1
GNDB1
GNDC1
V1-
CIRCUIT 1
CAPACITIVELY
COUPLED
ESD CLAMP
CIRCUIT 4A
LOGIC PIN
21k
+
1.2V
-
33k
V+
GND
V-
CIRCUIT 2
V2+
GNDA2
GNDB2
GNDC2
V2-
CAPACITIVELY
COUPLED
ESD CLAMP
CIRCUIT 4B
V+
OUT
V-
CIRCUIT 3
SUBSTRATE 1
V1-
~1MΩ
SUBSTRATE 2
V2-
~1MΩ
THERMAL HEAT SINK PAD
AC Test Circuits
V_IN
50Ω
or
75Ω
ISL59483
C_L
5pF
R_L
500Ω
FIGURE 42A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
ISL59483
R_S
V_IN
50Ω
C_L ^475Ω
50Ω
or
5pF
or
75Ω
75Ω
TEST
EQUIPMENT
50Ω
or
75Ω
FIGURE 42B. TEST CIRCUIT FOR MEASURING WITH 50Ω OR
75Ω INPUT TERMINATED EQUIPMENT
V_IN
50Ω
or
75Ω
ISL59483
R_S
C_L ^{50Ω or 75Ω}
5pF
TEST
EQUIPMENT
50Ω
or
75Ω
FIGURE 42C. BACKLOADED TEST CIRCUIT FOR VIDEO
CABLE APPLICATION. BANDWIDTH AND
LINEARITY FOR R_L LESS THAN 500Ω WILL BE
DEGRADED.
FIGURE 42. TEST CIRCUITS
Figure 42A illustrates the optimum output load for testing AC
performance. Figure 42B illustrates the optimum output load
when connecting to 50Ω input terminated equipment.
Application Information
General
The ISL59483 is ideal as the matrix element of high
performance switchers and routers. Key features include
high impedance buffered analog inputs and excellent AC
performance at output loads down to 150Ω for video cable-
driving. The current feedback output amplifiers are stable
operating into capacitive loads and bandwidth is optimized
with a load of 5pF in parallel with a 500Ω. Total output
capacitance can be split between the PCB capacitance and
an external load capacitor.
Ground Connections
For the best isolation and crosstalk rejection, all GND pins
must connect to the GND plane.
Power-up Considerations
The ESD protection circuits use internal diodes from all pins
the V+ and V- supplies. In addition, a dV/dT-triggered clamp
is connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dV/dT triggered clamp imposes a maximum
supply turn-on slew rate of 1V/µs. Damaging currents can
flow for power supply rates-of-rise in excess of 1V/µs, such
as during hot plugging. Under these conditions, additional
methods should be employed to ensure the rate of rise is not
exceeded.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic
input pins. Schottky diodes (Motorola MBR0550T or
equivalent) connected from V+ to ground and V- to ground
(Figure 43) will shunt damaging currents away from the
internal V+ and V- ESD diodes in the event that the V+
supply is applied to the device before the V- supply. One
Schottky can be used to protect both V+ power supply pins,
and a second for the protection of both V- pins.
13
FN6394.2
May 21, 2007