ISL28233_10 Datasheet, PDF (13/23 Pages) Intersil Corporation – Dual and Quad Micropower Chopper Stabilized, RRIO Operational Amplifiers

ISL28233, ISL28433
Applications Information
Functional Description
The ISL28233 and ISL28433 use a proprietary
chopper-stabilized technique (see Figure 39) that
combines a 400kHz main amplifier with a very high open
loop gain (174dB) chopper amplifier to achieve very low
offset voltage and drift (2µV, 0.01µV/°C typical) while
consuming only 18µA of supply current per channel.
This multi-path amplifier architecture contains a time
continuous main amplifier whose input DC offset is
corrected by a parallel-connected, high gain chopper
stabilized DC correction amplifier operating at 100kHz.
From DC to ~5kHz, both amplifiers are active with DC
offset correction and most of the low frequency gain is
provided by the chopper amplifier. A 5kHz crossover filter
cuts off the low frequency amplifier path leaving the
main amplifier active out to the 400kHz gain-bandwidth
product of the device.
The key benefits of this architecture for precision
applications are very high open loop gain, very low DC
offset, and low 1/f noise. The noise is virtually flat across
the frequency range from a few millihertz out to 100kHz,
except for the narrow noise peak at the amplifier
crossover frequency (5kHz).
Rail-to-rail Input and Output (RRIO)
The RRIO CMOS amplifier uses parallel input PMOS and
NMOS that enable the inputs to swing 100mV beyond
either supply rail. The inverting and non-inverting inputs
do not have back-to-back input clamp diodes and are
capable of maintaining high input impedance at high
differential input voltages. This is effective in eliminating
output distortion caused by high slew-rate input signals.
The output stage uses common source connected PMOS
and NMOS devices to achieve rail-to-rail output drive
capability with 17mA current limit and the capability to
swing to within 20mV of either rail while driving a 10kΩ
load.
IN+ and IN- Protection
All input terminals have internal ESD protection diodes
to both positive and negative supply rails, limiting the
input voltage to within one diode beyond the supply
rails. For applications where either input is expected to
exceed the rails by 0.5V, an external series resistor
must be used to ensure the input currents never exceed
20mA (see Figure 40).
-
R_IN
V_IN
+
R_L
V_OUT
FIGURE 40. INPUT CURRENT LIMITING
Layout Guidelines for High Impedance
Inputs
To achieve the maximum performance of the high input
impedance and low offset voltage of the ISL28233 and
ISL28433 amplifiers, care should be taken in the circuit
board layout. The PC board surface must remain clean
and free of moisture to avoid leakage currents between
adjacent traces. Surface coating of the circuit board will
reduce surface moisture and provide a humidity barrier,
reducing parasitic resistance on the board.
High Gain, Precision DC-Coupled Amplifier
The circuit in Figure 41 implements a single-stage
DC-coupled amplifier with an input DC sensitivity of
under 100nV that is only possible using a low VOS
amplifier with high open loop gain. High gain DC
amplifiers operating from low voltage supplies are not
practical using typical low offset precision op amps. For
example, a typical precision amplifier in a gain of 10kV/V
with a ±100µV V_OS and offset drift 0.5µV/°C of a low
offset op amp would produce a DC error of >1V with an
additional 5mV/°C of temperature dependent error
making it difficult to resolve DC input voltage changes in
the mV range.
The ±6µV max V_OS and 0.05µV/°C max temperature
drift of the ISL28233, ISL28433 produces a temperature
stable maximum DC output error of only ±60mV with a
maximum output temperature drift of 0.5mV/°C. The
additional benefit of a very low 1/f noise corner
frequency and some feedback filtering enables DC
voltages and voltage fluctuations well below 100nV to be
easily detected with a simple single stage amplifier.
C_F
0.018µF
1MΩ,
V_IN
100Ω
1MΩ
+2.5V
-
+
R_L
100Ω
-2.5V
V_OUT
A_CL = 10kV/V
FIGURE 41. HIGH GAIN, PRECISION DC-COUPLED
AMPLIFIER
ISL28233, ISL28433 SPICE Model
Figure 42 shows the SPICE model schematic and
Figure 43 shows the net list for the ISL28233, ISL28433
SPICE model. The model is a simplified version of the
actual device and simulates important parameters such
as noise, Slew Rate, Gain and Phase. The model uses
typical parameters from the “Electrical Specifications
Table” on page 4. The poles and zeroes in the model
were determined from the actual open and closed-loop
gain and phase response. This enables the model to
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FN7692.0
August 25, 2010