ISL23415_11 Datasheet, PDF (13/20 Pages) Intersil Corporation – Single, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23415
Typical Performance Curves (Continued)
CH1: 0.5V/DIV, 0.2µs/DIV RH PIN
1.2
CH2: 0.2V/DIV, 0.2µs/DIV RW PIN
1.0
0.8
V_CC = 5.5V, V_LOGIC = 5.5V
0.6
R_TOTAL = 10k
-3dB FREQUENCY = 1.4MHz AT MIDDLE TAP
FIGURE 23. 10k -3dB CUT OFF FREQUENCY
0.4
V_CC = 1.7V, V_LOGIC = 1.2V
0.2
0
-40
-15
10
35
60
85
110
TEMPERATURE (°C)
FIGURE 24. STANDBY CURRENT vs TEMPERATURE
Functional Pin Description
Potentiometers Pins
RH AND RL
The high (RH) and low (RL) terminals of the ISL23415 are
equivalent to the fixed terminals of a mechanical potentiometer.
The RH and RL are referenced to the relative position of the wiper
and not the voltage potential on the terminals. With the WR
register set to 255 decimal, the wiper will be closest to RH, and
with the WR register set to 0, the wiper is closest to RL.
RW
The RW is the wiper terminal, and it is equivalent to the
moveable terminal of a mechanical potentiometer. The position
of the wiper within the array is determined by the WR register.
Power Pins
V_CC
Power terminal for the potentiometer section analog power
source. Can be any value needed to support voltage range of DCP
pins, from 1.7V to 5.5V, independent of the V_LOGIC voltage.
Bus Interface Pins
SERIAL CLOCK (SCL)
This input is the serial clock of the SPI serial interface.
SERIAL DATA INPUT (SDI)
The SDI is a serial data input pin for SPI interface. It receives
operation code, wiper address and data from the SPI remote
host device. The data bits are shifted in at the rising edge of the
serial clock SCK, while the CS input is low.
SERIAL DATA OUTPUT (SDO)
The SDO is a serial data output pin. During a read cycle, the data
bits are shifted out on the falling edge of the serial clock SCK and
will be available to the master on the following rising edge of SCK.
The output type is configured through ACR[1] bit for Push-Pull or
Open Drain operation. Default setting for this pin is Push-Pull. An
external pull-up resistor is required for Open Drain output
operation. When CS is HIGH, the SDO pin is in tri-state (Z) or
high-tri-state (Hi-Z) depends on the selected configuration.
CHIP SELECT (CS)
CS LOW enables the ISL23415, placing it in the active power
mode. A HIGH to LOW transition on CS is required prior to the
start of any operation after power-up. When CS is HIGH, the
ISL23415 is deselected and the SDO pin is at high impedance,
and the device will be in the standby state.
V_LOGIC
Digital power source for the logic control section. It supplies an
internal level translator for 1.2V to 5.5V serial bus operation. Use
the same supply as the I²C logic source.
Principles of Operation
The ISL23415 is an integrated circuit incorporating one DCP with
its associated registers and an SPI serial interface providing
direct communication between a host and the potentiometer.
The resistor array is comprised of individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a “make before
break” mode when the wiper changes tap positions.
Voltage at any DCP pins, RH, RL or RW, should not exceed V_CC
level at any conditions during power-up and normal operation.
The V_LOGIC pin needs to be connected to the SPI bus supply
which allows reliable communication with the wide range of
microcontrollers and independent of the V_CC level. This is
extremely important in systems where the digital supply has
lower levels than the analog supply.
13
FN7780.1
August 16, 2011