ISL22317 Datasheet, PDF (13/15 Pages) Intersil Corporation – Precision Single Digitally Controlled Potentiometer (XDCP™)

ISL22317
SCL FROM
MASTER
1
SDA OUTPUT FROM
TRANSMITTER
8
9
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 22. ACKNOWLEDGE RESPONSE FROM RECEIVER
SIGNALS FROM
THE MASTER
WRITE
S
T
A _{IDENTIFICATION}
R
BYTE
T
ADDRESS
BYTE
S
DATA
T
BYTE
O
P
SIGNAL AT SDA
0 1 0 1 0 A1 0 0 0 0 0 0
SIGNALS FROM
THE SLAVE
A
A
A
C
C
C
K
K
K
FIGURE 23. BYTE WRITE SEQUENCE
S
S
SIGNALS T
T
FROM THE A IDENTIFICATION
A IDENTIFICATION
A
MASTER R
T
BYTE WITH
R/W=0
ADDRESS
BYTE
R _{BYTE WITH}
T
R/W=1
C
K
SIGNAL AT SDA 0 1 0 1 0 A1 0 0 0 0 0 0
A
SIGNALS FROM
C
THE SLAVE
K
0 1 0 1 0 A1 0 1
A
A
C
C _{FIRST READ}
K
K _{DATA BYTE}
FIGURE 24. READ SEQUENCE
A
C
K
S
AT
CO
KP
LAST READ
DATA BYTE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22317 responds with an ACK. At this time, the device
enters its standby state (see Figure 23). The non-volatile
write cycle starts after a STOP condition is determined and
requires up to 20ms delay for the next non-volatile write.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 24). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
13
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL22317 responds with an ACK. Then
the ISL22317 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a ACK and STOP condition) following the
last bit of the last Data Byte (see Figure 24).
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
FN6912.0
May 26, 2009