HC55180 Datasheet, PDF (13/19 Pages) Intersil Corporation – Extended Reach Ringing SLIC Family

HC55180, HC55181, HC55182, HC55183, HC55184
Logic Control
Ringing patterns consist of silent intervals. The ringing to
silent pattern is called the ringing cadence. During the silent
portion of ringing, the device can be programmed to any
other operating mode. The most likely candidates are low
power standby or forward active. Depending on system
requirements, the low or high battery may be selected.
Loop supervision is provided with the ring trip detector. The ring
trip detector senses the change in loop current when the phone
is taken off hook. The loop detector full wave rectifies the
ringing current, which is then filtered with external components
R_RT and C_RT. The resistor R_RT sets the trip threshold and the
capacitor C_RT sets the trip response time. Most applications will
require a trip response time less than 150ms.
Three very distinct actions occur when the devices detects a
ring trip. First, the DET output is latched low. The latching
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the VRS input is
disabled, removing the ring signal from the line. Third, the
device is internally forced to the forward active mode.
Power Dissipation
The power dissipation during ringing is dictated by the load
driving requirements and the ringing waveform. The key to valid
power calculations is the correct definition of average and RMS
currents. The average current defines the high battery supply
current. The RMS current defines the load current.
The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
power, P_r, and the silent interval power, P_s.
P_RNG= P_r × _t--_r----+^t--^r---_t-_s- + P_s × _t--_r----^t_+-^s----_t-_s-
(EQ. 33)
The terms t_R and t_S represent the cadence. The ringing
interval is t_R and the silent interval is t_S . The typical cadence
ratio t_R:t_S is 1:2.
The quiescent power of the device in the ringing mode is
defined in Equation 34.
P_r(Q) = V_BH × I_BHQ + V_BL × I_BLQ + V_CC × I_CCQ
(EQ. 34)
The total power during the ringing interval is the sum of the
quiescent power and loading power:
P_r = P_r(Q) + V_BH × I_AVG – -_Z---_R-----_E----_N^V-----^R2_+----^M-_R----^SL----_O----_O-----_P-
(EQ. 35)
For sinusoidal waveforms, the average current, I_AVG, is
defined in Equation 36.
I_AVG=


2_{-π-}
-_Z---_R---^V--_E--^R--_N--^M---+--^S---_R--^×--_L----_O---²-_O-----_P-
(EQ. 36)
The silent interval power dissipation will be determined by
the quiescent power of the selected operating mode.
Forward Loop Back
Overview
The forward loop back mode (FLB, 101) provides test
capability for the device. An internal signal path is enabled
allowing for both DC and AC verification. The internal 600Ω
terminating resistor has a tolerance of ±20%. The device is
intended to operate from only the low battery during this
mode.
Architecture
When the forward loop back mode is initiated internal
switches connect a 600Ω load across the outputs of the Tip
and Ring amplifiers.
TIP
RING
600Ω
TIP AMP
RING AMP
FIGURE 10. FORWARD LOOP BACK INTERNAL TERMINATION
DC Verification
When the internal signal path is provided, DC current will
flow from Tip to Ring. The DC current will force DET low,
indicating the presence of loop current. In addition, the ALM
output will also go low. This does not indicate a thermal
alarm condition. Rather, proper logic operation is verified in
the event of a thermal shutdown. In addition to verifying
device functionality, toggling the logic outputs verifies the
interface to the system controller.
AC Verification
The entire AC loop of the device is active during the forward
loop back mode. Therefore a 4-wire to 4-wire level test
capability is provided. Depending on the transhybrid balance
implementation, test coverage is provided by a one or two
step process.
System architectures which cannot disable the transhybrid
function would require a two step process. The first step
would be to send a test tone to the device while on hook and
not in forward loop back mode. The return signal would be
the test level times the gain R_F/R_A of the transhybrid
amplifier. Since the device would not be terminated,
cancellation would not occur. The second step would be to
program the device to FLB and resend the test tone. The
return signal would be much lower in amplitude than the first
step, indicating the device was active and the internal
termination attenuated the return signal.
System architectures which disable the transhybrid function
would achieve test coverage with a signal step. Once the
transhybrid function is disable, program the device for FLB
and send the test tone. The return signal level is determined
by the 4-wire to 4-wire gain of the device.
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