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X9250_14 Datasheet, PDF (12/20 Pages) Intersil Corporation – Quad Digitally Controlled Potentiometers
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X9250
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Symbol
Parameter
Limits
Min. Typ. Max.
Unit
Test Conditions
ICC1
ICC2
ISB
ILI
ILO
VIH
VIL
VOL
VCC supply current
(active)
VCC supply current
(nonvolatile write)
VCC current (standby)
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
VCC x 0.7
-0.5
400
µA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
1
mA fSCK = 2MHz, SO = Open,
Other Inputs = VSS
5
µA
SCK = SI = VSS, Addr. = VSS
10
µA
VIN = VSS to VCC
10
µA
VOUT = VSS to VCC
VCC + 0.1
V
VCC x 0.3
V
0.4
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
Years
CAPACITANCE
Symbol
COUT(5)
CIN(5)
Test
Output capacitance (SO)
Input capacitance (A0, A1, SI, and SCK, CS)
Max.
8
6
Unit
pF
pF
Test Conditions
VOUT = 0V
VIN = 0V
POWER-UP TIMING
Symbol
tPUR(6)
tPUW(6)
tR VCC(7)
Parameter
Power-up to initiation of read operation
Power-up to initiation of write operation
VCC power up ramp rate
Min.
0.2
Max.
1
5
50
Unit
ms
ms
V/msec
POWER UP AND DOWN REQUIREMENT
The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach
their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The VCC ramp rate spec is always in effect.
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can be
issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing level
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
12
FN8165.3
August 29, 2006
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