KAD2708C_11 Datasheet, PDF (12/16 Pages) Intersil Corporation – 8-Bit, 275/210/170/105MSPS A/D Converter

KAD2708C
Functional Description
The KAD2708 is an 8-bit, 275MSPS A/D converter in a
pipelined architecture. The input voltage is captured by a
sample & hold circuit and converted to a unit of charge.
Proprietary charge domain techniques are used to compare
the input to a series of reference charges. These
comparisons determine the digital code for each input value.
The converter pipeline requires 24 sample clocks to produce
a result. Digital error correction is also applied, resulting in a
total latency of 28 clock cycles. This is evident to the user as
a latency between the start of a conversion and the data
being available on the digital outputs.
At start-up, a self-calibration is performed to minimize gain
and offset errors. The reset pin (RST) is initially held low
internally at power-up and will remain in that state until the
calibration is complete. The clock frequency should remain
fixed during this time.
Calibration accuracy is maintained for the sample rate at
which it is performed, and therefore should be repeated if the
clock frequency is changed by more than 10%. Recalibration
can be initiated via the RST pin, or power cycling, at any
time.
Reset
Recalibration of the ADC can be initiated at any time by
driving the RST pin low for a minimum of one clock cycle. An
open-drain driver is recommended.
The calibration sequence is initiated on the rising edge of
RST, as shown in Figure 21. The over-range output (OR) is
set high once RST is pulled low, and remains in that state
until calibration is complete. The OR output returns to
normal operation at that time, so it is important that the
analog input be within the converter’s full-scale range in
order to observe the transition. If the input is in an
over-range state the OR pin will stay high and it will not be
possible to detect the end of the calibration cycle.
While RST is low, the output clock (CLKOUT) stops toggling
and is set low. Normal operation of the output clock resumes
at the next input clock edge (CLKP/CLKN) after RST is de-
asserted. At 275MSPS the nominal calibration time is
~240ms.
CLKN
CLKP
RST
OR
CLKOUT
Calibration Time
Calibration Begins
Calibration Complete
Voltage Reference
The VREF pin is the full-scale reference, which sets the
full-scale input voltage for the chip and requires a bypass
capacitor of 0.1µF or larger. An internally generated
reference voltage is provided from a bandgap voltage buffer.
This buffer can sink or source up to 50µA externally.
An external voltage may be applied to this pin to provide a
more accurate reference than the internally generated
bandgap voltage or to match the full-scale reference among
a system of KAD2708C chips. One option in the latter
configuration is to use one KAD2708C's internally generated
reference as the external reference voltage for the other
chips in the system. Additionally, an externally provided
reference can be changed from the nominal value to adjust
the full-scale input voltage within a limited range.
To select whether the full-scale reference is internally
generated or externally provided, the digital input port
VREFSEL should be set appropriately, low for internal or
high for external.This pin also has an internal 18kΩ pull-up
resistor. To use the internally generated reference,
VREFSEL can be tied directly to AVSS, and to use an
external reference, VREFSEL can be left unconnected.
Analog Input
The fully differential ADC input (INP/INN) connects to the
sample and hold circuit. The ideal full-scale input voltage is
1.5V_PP, centered at the VCM voltage of 0.86V as shown in
Figure 22.
V
1.8
1.4
INP
0.75V
INN
VCM
1.0
0.86V
0.6
-0.75V
0.2
t
FIGURE 22. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are
driven differentially in an AC-coupled configuration. The
common-mode output voltage, VCM, should be used to
properly bias each input as shown in Figures 23 and 24. An
RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate
frequency (IF) inputs. The recommended biasing is shown in
Figures 23 and 24.
FIGURE 21. CALIBRATION TIMING
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FN6812.1
April 14, 2011