ISL80111_15 Datasheet, PDF (12/17 Pages) Intersil Corporation – Ultra Low Dropout 1A, 2A, 3A Low Input Voltage NMOS LDOs

ISL80111, ISL80112, ISL80113
Typical Operating Performance Unless otherwise noted, V_IN = 1.8V, V_BIAS = 3.3V, V_OUT = 1.2V, C_IN = C_OUT = 10µF,
T_J = +25°C, I_LOAD = 0A. (Continued)
3.0
1000
2.5
300 lfm
2.0
1.5
1.0
0 lfm
0.5
100
10
V_BIAS = 3.8V
V_IN = 1.28V
1 V_OUT = 1V
I_OUT = 3A
V_BIAS = 5V
V_IN = 3.8V
V_OUT = 3.3V
I_OUT = 3A
0.0
25 30 35 40 45 50 55 60 65 70 75 80 85 105 125
TEMPERATURE (°C)
0.1
0.1
1
10
100
1k
10k 100k
FREQUENCY (Hz)
FIGURE 35. CONTINUOUS POWER LIMIT vs AIR TEMP AND FLOW
FIGURE 36. INPUT VOLTAGE NOISE vs BIAS VOLTAGE
Functional Description
The ISL80111, ISL80112 and ISL80113 are high-performance,
low-dropout regulators featuring an NMOS pass device. Benefits
of using an NMOS as a pass device include low input voltage,
stability over a wide range of output capacitors, and ultra low
dropout voltage. The ISL80111, ISL80112 and ISL80113 are
ideal for post regulation of switch mode power supplies.
The ISL80111, ISL80112 and ISL80113 also integrate enable,
power-good indicator, current limit protection, and thermal
shutdown functions into a space-saving 3x3 DFN package.
Input Voltage Requirements
The VIN pin provides the high current to the drain of the NMOS
pass transistor. The specified minimum input voltage is 1V and
dropout voltage for this family of LDOs has been conservatively
specified.
Bias Voltage Requirements
The V_BIAS input powers the internal control circuits, reference
voltage, and LDO gate driver. The difference between the V_BIAS
voltage and the output voltage must be greater than the V_BIAS
dropout voltage specified in the “Electrical Specifications” table
beginning on Page 4. The minimum V_BIAS input is 2.9V.
Enable Operation
The ENABLE turn-on threshold is typically 600mV with a
hysteresis of 100mV. This pin must not be left floating. When this
pin is not used, it must be tied to V_BIAS. A 1kΩ to 10kΩ pull-up
resistor is required for applications that use open collector or
open drain outputs to control the ENABLE pin.
Soft-start Operation
The ISL8011x has an internal 100µs typical soft-start function to
prevent excessive in-rush current during start-up.
Power-good Operation
The PGOOD flag is an open-drain NMOS that can sink up to 10mA
during a fault condition. Applications not using this feature must
connect this pin to ground. The PGOOD pin requires an external
pull-up resistor, which is typically connected to the V_OUT pin. The
PGOOD pin should not be pulled up to a voltage source greater
than V_BIAS. A PGOOD fault can be caused by the output voltage
going below 84% of the nominal output voltage. PGOOD does not
function during thermal shutdown as the V_OUT is less than the
minimum regulation voltage during that time.
Output Voltage Selection
An external resistor divider is used to scale the output voltage
relative to the internal reference voltage. This voltage is then fed
back to the error amplifier. The output voltage can be
programmed to any level between 0.8V and 4V. Referring to
Figure 1 the external resistor divider, R₃ and R₄, is used to set
the output voltage as shown in Equation 1. The recommended
value for R₄ is 500Ω to 1kΩ. R₃ is then chosen according to
Equation 2.
V_OUT
=
0.5 V
×
⎛
⎜
⎝
-^R----³-
R₄
+
⎞
1⎟
⎠
(EQ. 1)
R₃
=
R₄
×
⎛
⎝
-^V----^O----^U----^T--
0.5 V
–
1_⎠⎞
(EQ. 2)
Current Limit Protection
The ISL80111, ISL80112, and ISL80113 incorporate protection
against overcurrent due to a short, overload condition applied to
the output and the in-rush current that occurs at start-up. The
LDO performs as a constant current source when the output
current exceeds the current limit threshold noted in “Electrical
Specifications” on page 4. If the short or overload condition is
removed from V_OUT, then the output returns to normal voltage
mode regulation. In the event of an overload condition, the LDO
might begin to cycle on and off due to the die temperature
exceeding the thermal fault condition.
Thermal Fault Protection
If the die temperature exceeds (typically) +160°C, the LDO
output shuts down until the die temperature cools to (typically)
+140°C. The level of power, combined with the thermal
impedance of the package (+48°C/W), determines whether the
junction temperature exceeds the thermal shutdown
temperature.
12
FN7841.2
November 1, 2013