ISL6752AAZA-T Datasheet, PDF (12/16 Pages) Intersil Corporation – ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control

ISL6752
Determine the amount of voltage, V_e, that must be added to
the current feedback signal using Equation 13.
V_e = 153mV
Next, determine the effect of the magnetizing current from
Equation 18.
ΔV_CS = 91mV
Using Equation 21, solve for the summing resistor, R9, from
CTBUF to CS.
R9 = 30.1kΩ
Determine the new value of R_CS, R’_CS, using Equation 22.
R’_CS = 15.4Ω
This discussion determines the minimum external ramp that
is required. Additional slope compensation may be
considered for design margin.
If the application requires deadtime of less than about
500ns, the CTBUF signal may not perform adequately for
slope compensation. CTBUF lags the CT sawtooth
waveform by 300ns to 400ns. This behavior results in a
non-zero value of CTBUF when the next half-cycle begins
when the deadtime is short.
Under these situations, slope compensation may be added
by externally buffering the CT signal as shown in Figure 7.
1
2 VREF
3
ISL6752
4
5
6
R9
7 CT
8 CS
R6
RCS
C4
CT
FIGURE 7. ADDING SLOPE COMPENSATION USING CT
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that Equations 20
and 21 require modification. Equation 20 becomes:
V_e – ΔV_CS
=
-²----^D------^â‹---^R-----⁶---
R6 + R9
V
(EQ. 23)
and Equation 21 becomes:
R9
=
-⁽--²----^D------–----^V----^e-----+-----^Δ----^V----^C----^S----⁾----^â‹---^R----⁶--
V_e – ΔV_CS
Ω
(EQ. 24)
The buffer transistor used to create the external ramp from
CT should have a sufficiently high gain (>200) so as to
minimize the required base current. Whatever base current
is required reduces the charging current into CT and will
reduce the oscillator frequency.
ZVS Full-Bridge Operation
The ISL6752 is a full-bridge zero-voltage switching (ZVS)
PWM controller that behaves much like a traditional hard
switched topology controller. Rather than drive the diagonal
bridge switches simultaneously, the upper switches (OUTUL,
OUTUR) are driven at a fixed 50% duty cycle and the lower
switches (OUTLL, OUTLR) are pulse width modulated on
the trailing edge.
CT
DEADTIME
OUTLL
OUTLR
PWM
PWM
PWM
PWM
OUTUR
RESONANT
DELAY
OUTUL
RESDEL
WINDOW
FIGURE 8. BRIDGE DRIVE SIGNAL TIMING
To understand how the ZVS method operates, one must
include the parasitic elements of the circuit and examine a
full switching cycle.
VIN+
UL
UR
D1
LL
VOUT+
LL
LR
D2
RTN
VIN-
FIGURE 9. IDEALIZED FULL-BRIDGE
In Figure 9, the power semiconductor switches have been
replaced by ideal switch elements with parallel diodes and
capacitance, the output rectifiers are ideal, and the
transformer leakage inductance has been included as a
discrete element. The parasitic capacitance has been
lumped together as switch capacitance, but represents all
parasitic capacitance in the circuit including winding
12
FN9181.3
October 31, 2008