ISL6532A Datasheet, PDF (12/17 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

ISL6532A
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
250kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit board design minimizes these
voltage spikes.
As an example, consider the turn-off transition of the control
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET. Any
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide traces minimizes the magnitude of voltage
spikes.
There are two sets of critical components in the ISL6532A
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are
the small signal components which connect to sensitive
nodes or supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended. Figure 4
shows the connections of the critical components in the
converter. Note that capacitors C_IN and C_OUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
In order to dissipate heat generated by the internal V_TT
LDO, the ground pad, pin 29, should be connected to the
internal ground plane through at least four vias. This allows
the heat to move away from the IC and also ties the pad to
the ground plane through a low impedance path.
The switching components should be placed close to the
ISL6532A first. Minimize the length of the connections between
the input capacitors, C_IN, and the power switches by placing
them nearby. Position both the ceramic and bulk input
capacitors as close to the upper MOSFET drain as possible.
12V_ATX
P12V
GNDP
ISL6532A
NCH
C_BP
V_{IN_DDR}
P5VSBY
5VSBY
C_BP
GNDP
UGATE
PHASE
5VSBY
C_IN
Q₁ ^LOUT
V_DDQ
LGATE
COMP
FB
Q₂
C₂
R₂
C₁
R₁
R₄ ^{C3 R}3
C_OUT1
VDDQ(3)
VTT(2)
V_DDQ
V_TT
C_OUT2
DRIVE2
FB2
GND PAD
R₅
R₆
V_{IN_AGP}
Q₃
V_AGP
C_OUT3
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
Position the output inductor and output capacitors between the
upper and lower MOSFETs and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB pin
with vias tied straight to the ground plane as required.
Feedback Compensation - PWM Buck Converter
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V_OUT) is regulated to the Reference voltage level. The error
amplifier output (V_E/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V_IN at the PHASE node.
The PWM wave is smoothed by the output filter (L_O and C_O).
12
FN9099.5
May 5, 2008