ISL6217A_14 Datasheet, PDF (12/20 Pages) Intersil Corporation – Precision Multi-Phase Buck PWM Controller for Intel, Mobile Voltage Positioning IMVP-IV and IMVP-IV+

ISL6217A
A logic low signal present on STPCPU# (pin DSEN#), with a
logic low signal on DPRSLPVR (pin DRSEN), signals the
ISL6217A to reduce the CORE output voltage to the Deep
Sleep level, the voltage on the DSV pin, and to operate in
diode emulation.
A logic high on DPRSLPVR, (pin DRSEN) with a logic low
signal on STPCPU# (pin DSEN#), signals the ISL6217A
controller to further reduce the CORE output voltage to the
Deeper Sleep level, which is the voltage on the DRSV pin.
Deep Sleep and Deeper Sleep voltage levels are
programmable and are explained in the “STV, DSV and
DRSV” section of this document.
Deep Sleep Enable-DSEN# and Deeper Sleep
Enable - DRSEN
Table 2 shows logic states controlling modes of operation.
Figure 6 and Figure 7 show the timing for transitions entering
and exiting Deep Sleep Mode and Deeper Sleep Mode. This
is controlled by the system signals STPCPU# and
DPRSLPVR. ISL6217A pins DSEN#, (Deep Sleep Enable #)
and DRSEN, (Deeper Sleep Enable), are connected to these
2 signals, respectively.
When DSEN# is logic high, and DRSEN is logic low, the
controller will operate in Active Mode and regulate the output
voltage to the VID commanded DAC voltage, minus the
voltage “Droop” as determined by the load current. Voltage
“Droop” is the reduction of output voltage proportional to
output current.
When a logic low is detected at the DSEN# and DRSEN
pins, the controller will regulate the output voltage to the
voltage seen on the DSV pin minus “Droop”. If the PWRCH
pin is connected to the DSEN# pin then the controller will
also switch to single channel operation.
When DSEN# is logic low and DRSEN is logic high the
controller will operate in Deeper Sleep mode. The ISL6217A
will then regulate to the voltage at the DRSV pin minus
“Droop”. If the PWRCH pin is connected to the DSEN# pin,
then the controller will also automatically switch to single
channel operation.
If the PWRCH pin is connected to an inverted DPRSLPVR
system signal, then the controller will automatically switch to
single channel operation during Deeper Sleep mode only.
Deep and Deeper Sleep voltage levels are programmable
and explained in the “STV, DSV and DRSV” section of this
document.
STV, DSV and DRSV
Start-up “Boot” Voltage - STV
The Start-up or “Boot” voltage is programmed by an external
resistor divider network from the OCSET pin. Refer to
Figure 8. Internally, a 1.75V reference voltage is output on
the OCSET pin. The start-up voltage is set through a voltage
divider from the 1.75V reference at the OCSET pin. The
voltage on the STV pin will be the voltage the controller will
regulate to during the start-up sequence.
Once the PGOOD pin of the ISL6217A controller is
externally enabled high by the Vccp and Vcc_mch
controllers, the ISL6217A will then ramp, after a 10µs delay,
to the voltage commanded by the VID setting minus “Droop”.
BATTERY
V_REF = 1.75V
I_OCSET
ISL6217A
OCSET
36.5K
R1
VBAT
1.200V _STV
VID COMMAND
R2 ^30.1K
DACOUT
VOLTAGE
0.750V _DRSV
1.21K
R3 ^49.9K
SOFT
DSV
GND
98.8%
DACOUT
98.8K
0.012µF
FIGURE 8. CONFIGURATIONS FOR BATTERY INPUT,
OVERCURRENT SETTING AND START, DEEP
SLEEP AND DEEPER SLEEP VOLTAGE
DIVIDERS
Deep Sleep Voltage - DSV
The Deep Sleep voltage is programmed by an external
voltage divider network from the DACOUT pin. Refer to
Figure 8. The DACOUT pin is the output of the VID digital-to-
analog converter. By having the Deep Sleep voltage setup
from a resistor divider from DAC, the Deep Sleep voltage will
be a constant percentage of the VID. Through the voltage
divider network, Deep Sleep voltage is set to 98.8% of the
programmed VID voltage, as per the IMVP-IV™ and
IMVP-IV+™ specification.
The IC enters the Deep Sleep mode when the DSEN# is low
and the DRSEN pin is low as shown in Figure 6 and
Figure 7. Once in Deep Sleep Mode, the controller will
regulate to the voltage seen on the DSV pin minus “Droop”.
Deeper Sleep Voltage - DRSV
The Deeper Sleep voltage, DRSV, is programmed by an
external voltage divider network from the 1.75V reference on
the OCSET pin. Refer to Figure 8. In Deeper Sleep mode
the ISL6217A controller will regulate the output voltage to
the voltage present on the DRSV pin minus “Droop”. This
voltage is easily changed by changing the ratio of R₁, R₂,
and R₃.
The IC enters Deeper Sleep mode when DRSEN is high and
DSEN# is low, as shown in Figure 7.
12
FN9107.3
June 30, 2005