ISL59920 Datasheet, PDF (12/16 Pages) Intersil Corporation – Triple Analog Video Delay Lines

SENABLE
SCLOCK
ISL59920, ISL59921, ISL59922, ISL59923
t_{SEN_SETUP}
t_{SEN_CYCLE}
SDATA
0
A1
A0
D4
D3
D2
D1
D0*
*D0 is 0 when addressing the test register a
b
v
w
x
y
z
FIGURE 33. SERIAL TIMING
Figure 32 shows the ISL5992x block diagram. The 3 analog
inputs are ground referenced single-ended signals. After the
signal is received, the delay is introduced by switching filter
blocks into the signal path. Each filter block is an all-pass
filter introducing either 1, 1.5 or 2ns of delay. In addition to
adding delay, each filter block also introduces some low
pass filtering. As a result, the bandwidth of the signal path
decreases from the 0ns delay setting to the maximum delay
setting, as shown in Figures 2 through 9 of the “Typical
Performance Curves”.
In operation, it is best to allocate the most delayed signal
0ns delay then increase the delay on the other channels to
bring them into line. This will result in delay compensation
with the lowest power and distortion.
TABLE 2. SERIAL BUS DATA (Continued)
vwxyz
ISL59920
DELAY
ISL59921 ISL59922 ISL59923
DELAY
DELAY
DELAY
00100
8
6
4
8
00101
10
7.5
5
10
00110
12
9
6
12
00111
14
10.5
7
14
01000
16
12
8
16
01001
18
13.5
9
18
01010
20
15
10
20
01011
22
16.5
11
22
01100
24
18
12
24
Serial Bus Operation
01101
26
19.5
13
26
The ISL5992x is programmed via 8-bit words sent through
its serial interface. The first bit (MSB) of SDATA is latched on
the first falling clock edge after SENABLE goes low, as
shown in Figure 33. This bit should be a 0 under all
conditions. The next two bits determine the color register to
be written to: 01 = R, 02 = G, and 03 = B (00 is reserved for
the test register). The final five bits set the delay for the
specified color. After 8 bits are latched, any additional clocks
are treated as a new word (data is shifted directly to the final
registers as it is clocked in). This allows the user to write (for
example) the 24 bits of data necessary for R, G, and B as a
single 24-bit word. It is the user's responsibility to send
complete multiples of 8 clock cycles. The serial state
machine is reset on the falling edge of SENABLE, so any
data corruption that may have occurred due to too many or
too few clocks can be corrected with a new word with the
correct number of clocks. The initial value of all registers on
power-up is 0.
01110
28
01111
30
10000
32
10001
34
10010
36
10011
38
10100
40
10101
42
10110
44
10111
46
11000
48
11001
50
11010
52
11011
54
21
14
28
22.5
15
30
24
16
N/A
25.5
17
N/A
27
18
N/A
28.5
19
N/A
30
20
N/A
31.5
21
N/A
33
22
N/A
34.5
23
N/A
36
24
N/A
37.5
25
N/A
39
26
N/A
40.5
27
N/A
TABLE 2. SERIAL BUS DATA
11100
56
42
28
N/A
vwxyz
00000
00001
00010
00011
ISL59920
DELAY
0
2
4
6
ISL59921
DELAY
0
1.5
3
4.5
ISL59922
DELAY
0
1
2
3
ISL59923
DELAY
0
2
4
6
11101
58
43.5
29
N/A
11110
60
45
30
N/A
11111
62
46.5
31
N/A
NOTE: Delay register word = 0abvwxyz; Red register - ab = 01;
Green register - ab = 10; Blue register - ab = 11; vwxyz selects
delay; ab = 00 writes to the test register to change the DAC slice
level.
12
FN6826.2
August 31, 2010