ISL5729 Datasheet, PDF (12/13 Pages) Intersil Corporation – Dual 10-bit, +3.3V, 130/210MSPS, CommLink TM High Speed D/A Converter

ISL5729
R_A=R_B=50Ω, R_DIFF=100Ω, assuming R_LOAD=50Ω. The
performance of Figure 13 and Figure 14 is basically the
same, however leaving the center tap of Figure 14 floating
allows the circuit to find a more balanced virtual ground,
theoretically improving the even order harmonic rejection,
but likely reducing the signal swing available due to the
output voltage compliance range limitations.
R_EQ = 0.5 x (R_LOAD // R_DIFF)
AT EACH OUTPUT
ISL5729
OUTA
R_DIFF
OUTB
V_OUT = (2 x OUTA x R_EQ)V
1:1
R_LOAD
R_LOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
R_EQ = 0.5 x (R_LOAD // R_DIFF// R_A), WHERE R_A=R_B
AT EACH OUTPUT
ISL5729
OUTA
OUTB
R_A
R_DIFF
R_B
V_OUT = (2 x OUTA x R_EQ)V
R_LOAD
R_LOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 14. ALTERNATIVE OUTPUT LOADING
Propagation Delay
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 15.
Test Service
Intersil offers customer-specific testing of CommLink
converters with a service called Testdrive. To submit a
request, fill out the Testdrive form at
www.intersil.com/testdrive. Or, send a request to the
technical support center.
Timing Diagram
CLK
D9-D0
t_PW1
t_PW2
t_SU
W₀
t_HLD
t_SU
W₁
t_HLD
t_SU
W₂
t_HLD
50%
W₃
I_OUT
t_PD
OUTPUT=W_-1
t_PD
OUTPUT=W₀
OUTPUT=W₁
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
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