HIP6020A Datasheet, PDF (12/16 Pages) Intersil Corporation – Advanced Dual PWM and Dual Linear Power Controller

HIP6020A
gain. Check the compensation gain at F_P2 with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 12 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
100
F_Z1
F_Z2 F_P1 F_P2
OPEN LOOP
ERROR AMP GAIN
80
20
log



-_V---^V-_P----^I-–-^N----_P--_{}
60
40
COMPENSATION
GAIN
20
0
-20
20 log


RR_-----21_{--}
MODULATOR
-40
GAIN
F_LC F_ESR
CLOSED LOOP
GAIN
-60
10
100
1K 10K 100K 1M 10M
FREQUENCY (Hz)
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45 degrees. Include worst case component variations when
determining phase margin.
PWM2 Controller Feedback Compensation
To reduce the number of external small-signal components
required by a typical application, the standard PWM
controller is internally stabilized. The only stability criteria
that needs to be met relates the minimum value of the output
inductor to the equivalent ESR of the output capacitor bank,
as shown in the following equation:
L_OUT(MIN) = ^E-----^S----^R-₂----^O-_×---^U--_π---^T--_×--^×--_B---¹--_W--⁰---¹---^.-⁷---⁵--
where
L_OUT(MIN) - minimum output inductor value at full output
current
ESR_OUT - equivalent ESR of the output capacitor bank
BW - desired converter bandwidth (not to exceed 0.25 to
0.30 of the switching frequency)
The design procedure for this output should follow the
following steps:
1. Choose number and type of output capacitors to meet the
output transient requirements based on the dynamic
loading characteristics of the output.
2. Determine the equivalent ESR of the output capacitor
bank and calculate minimum output inductor value.
3. Verify that chosen inductor meets this minimum value crite-
ria (at full output load). As inductors tend to saturate as the
current increases, it is recommended the chosen output in-
ductor be no more than 30% saturated at full output load.
Oscillator Synchronization
The PWM controllers use a triangle wave for comparison
with the error amplifier output to provide a pulse-width
modulated signal. Should the output voltage of the two
converters be programmed close to each other, then cross-
talk between the converters could cause non-uniform
PHASE pulse-widths and increased output voltage ripple.
The HIP6020A avoids this problem by appropriately
synchronizing the two converters for 1.5V AGP output
voltage setting. Thus, for core output voltage settings less
than 2.4V, PWM1 operates out of phase with PWM2.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output capacitor
to filter the current ripple. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
PWM Output Capacitors
Modern microprocessors produce transient load rates
above 1A/ns. High frequency capacitors initially supply the
transient current and slow the load rate-of-change seen by
the bulk capacitors. The bulk filter capacitor values are
generally determined by the ESR (effective series
resistance) and voltage rating requirements rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage and
the initial voltage drop following a high slew-rate transient’s
edge. An aluminum electrolytic capacitor’s ESR value is
related to the case size with lower ESR available in larger
case sizes. However, the equivalent series inductance (ESL)
of these capacitors increases with case size and can reduce
the usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter. Work
with your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
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