HIP4081 Datasheet, PDF (12/18 Pages) Intersil Corporation – 80V/2.5A Peak, High Frequency Full Bridge FET Driver

HIP4081
Typical Performance Curves V_DD = V_CC = V_AHB = V_BHB = 12V, V_SS = V_ALS = V_BLS = V_AHS = V_BHS = 0V,
R_HDEL = R_LDEL = 100K and T_A = 25^oC, Unless Otherwise Specified (Continued)
1000
150
500
120
200
100
90
50
20
60
10
80V
5
2
1
12
5 10 20
60V
40V
20V
50 100 200
500 1000
30
0
10
50
100
150
200
250
SWITCHING FREQUENCY (kHz)
HDEL/LDEL RESISTANCE (kΩ)
FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs
FREQUENCY AND BUS VOLTAGE
FIGURE 29. MINIMUM DEAD-TIME vs DEL RESISTANCE
HI4081 Power-up Application Information
The HIP4081 H-Bridge Driver IC requires external circuitry
to assure reliable start-up conditions of the upper drivers. If
not addressed in the application, the H-bridge power MOS-
FETs may be exposed to shoot-through current, possibly
leading to MOSFET failure. Following the instructions below
will result in reliable start-up.
The HIP4081 has four inputs, one for each output. Outputs
ALO and BLO are directly controlled by input ALI and BLI.
By holding ALI and BLI low during start-up no shoot-through
conditions can occur. To set the latches to the upper drivers
such that the driver outputs, AHO and BHO, are off, the DIS
pin must be toggled from low to high after power is applied.
This is accomplished with a simple resistor divider, as shown
below in Figure 30. As the V_DD/V_CC supply ramps from zero
up, the DIS voltage is below its input threshold of 1.7V due
to the R1/R2 resistor divider. When V_DD/V_CC exceeds
approximately 9V to 10V, DIS becomes greater than the
input threshold and the chip disables all outputs. It is critical
that ALI and BLI be held low prior to DIS reaching its thresh-
old level of 1.7V while V_DD/V_CC is ramping up, so that shoot
through is avoided. After power is up the chip can be
enabled by the ENABLE signal which pulls the DIS pin low.
R1
15K
ENABLE
R2
3.3K
1 BHB
2 BHI
3 DIS
4 V_SS
5 BLI
6 ALI
7 AHI
8 HDEL
9 LDEL
10 AHB
BHO 20
BHS 19
BLO 18
BLS 17
V_DD 16
V_CC 15
ALS 14
ALO 13
AHS 12
AHO 11
FIGURE 30A.
V_DD
ALI, BLI
DIS
12V, FINAL VALUE
8.5V TO 10.5V (ASSUMES 5% RESISTORS)
1.7V
t1
NOTES:
2. ALI and/or BLI may be high after t1, whereupon the ENABLE pin
may also be brought high.
3. Another product, HIP4081A, incorporates undervoltage circuitry
which eliminates the need for the above power up circuitry.
FIGURE 30B. TIMING DIAGRAM FOR FIGURE 30A
12