EL5173_08 Datasheet, PDF (12/15 Pages) Intersil Corporation – 450MHz Differential Twisted-Pair Drivers

EL5173, EL5373
Maximum reliability is maintained if the output current never
exceeds ±60mA. This limit is set by the design of the internal
metal interconnect.
Power Dissipation
With the high output drive capability of the EL5173 and
EL5373 it is possible to exceed the +125°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if the load conditions or package types need to be
modified for the amplifier to remain in the safe operating
area.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
PD_MAX
=
T_{----J---M-----A----X-----–-----}T_{----A---M-----A----X--}
Θ_JA
(EQ. 1)
Where:
• T_JMAX = Maximum junction temperature
• T_AMAX = Maximum ambient temperature
• θ_JA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
PD
=
i
×
⎛
⎜
⎝
V_S
×
I_SMAX
+
V_S
×
Δ_-R----V_{-L---DO-- ⎠⎟⎞}
(EQ. 2)
Typical Applications
Twisted pair cable driver
Where:
• V_S = Total supply voltage
• I_SMAX = Maximum quiescent supply current per channel
• ΔV_O = Maximum differential output voltage of the
application
• R_LD = Differential load resistance
• I_LOAD = Load current
• i = Number of channels
By setting the two PD_MAX equations equal to each other, we
can solve the output current and R_LOAD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the V_S- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from V_S+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the V_S- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier’s inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
0Ω
EL5173/
EL5373
50
50Ω
50
Z_O = 100Ω
50Ω
V_FB
V_IN
EL5175/
EL5375
V_INB
V_REF
V_OUT
FIGURE 23. TWISTED PAIR CABLE DRIVER
12
FN7312.7
February 4, 2008