ZL1505_10 Datasheet, PDF (11/13 Pages) Intersil Corporation – Synchronous Step-Down MOSFET Drivers

ZL1505
ZL1505 Overview
Theory of Operation
The ZL1505 is a synchronous N-channel MOSFET driver
that is intended for use with Zilker Labs Digital-DC PWM
controllers to enable a high-efficiency DC/DC conversion
scheme. The patented Digital-DC control scheme utilizes
a closed-loop algorithm to optimize the dead-time
applied between the gate drive signals for the high-side
and low-side MOSFETs. By monitoring the duty cycle of
the resulting DC/DC converter circuit, this dynamic
routine continuously varies the MOSFET dead times to
optimize conversion efficiency in response to varying
circuit conditions. The ZL1505’s dual PWM input
configuration enables this optimization scheme to be
applied while minimizing the complexity within the driver
device. Please refer to the ZL2004 data sheet for details
on the dynamic dead-time optimization routine.
The ZL1505 integrates two powerful gate drivers that
have been optimized for step-down DC/DC conversion
circuit configurations whose output current can exceed
40A per phase. The ZL1505 also integrates a 30V
bootstrap Schottky diode to minimize the external
components and provide a high drive voltage to the
high-side driver device.
Variable Gate Drive Current
The ZL1505 incorporates an innovative variable drive
current scheme that enables the user to optimize the
gate drive current levels to the requirements of the
external MOSFETs used over a wide range of operating
frequencies. Each of the gate drivers incorporates a logic
input (HSEL and LSEL) that allows the user to select the
gate drive strength to 50% or 100% of the total rated
drive current.
With the HSEL pin connected to the BST pin, the
high-side driver can deliver the full rated gate drive
current; with the HSEL pin connected to the SW pin, the
output current will be limited to 50% of the full rated
output capability. With the LSEL pin connected to VDD,
the low-side driver can deliver the full rated gate drive
current; with the LSEL pin connected to GND, the output
current will be limited to 50% of the full rated output
capability. Using HSEL and LSEL, the ZL1505 can be used
across a wide range of applications using only a simple
PCB layout change.
Also, the VDD pin is the gate drive bias supply for the
external MOSFETs. VDD can be used to vary the gate
drive strength as shown for the low-side driver in
Figures 9 thru 12 and for the high-side driver in
Figures 17 thru 20.
Overlap Protection Circuit
The ZL1505 includes an internal watchdog circuit that
prevents excessive shoot-through current from occurring
in the unlikely event that the PWM converter places both
switches in the ON position. If the overlap time between
the PWMH and PWML pulses exceeds 30ns, the PWMH
signal will be forced to the LOW state until the overlap
condition ceases, allowing normal switching operation to
continue.
Start-up Requirements
During power-up, the ZL1505 maintains both GH and GL
outputs in the LOW state while the V_IN voltage is
ramping up. Once the V_DD supply is within specification,
the GH and GL pins may be operated using the PWMH
and PWML logic inputs respectively.
In the case where the PWM controller is powered from a
supply other than the ZL1505’s V_DD supply, and the PWM
controller is powered up first, the PWM controller gate
outputs should be kept in low or in high-impedance state
until the V_DD supply is within specification. Additionally, if
the ZL1505 begins its power-down sequence prior to the
PWM controller then the PWM controller gate outputs
should be set in low or in high-impedance state before
the V_DD voltage supply drops below its specified range.
Thermal protection
When the junction temperature exceeds +150°C the
high-side driver output GH is forced to logic low state.
The driver output is allowed to switch logic states again
once the junction temperature drops below +134°C.
11
FN6845.2
November 12, 2010