X5163S Datasheet, PDF (11/21 Pages) Intersil Corporation – CPU Supervisor with 16Kbit SPI EEPROM

X5163, X5165
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION
DATA BYTE
7 6 5 43 2 1 0
SO
HIGH IMPEDANCE
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE WILL CHANGE
FROM LOW TO FROM LOW TO
HIGH
HIGH
MAY CHANGE WILL CHANGE
FROM HIGH TO FROM HIGH TO
LOW
LOW
DON’T CARE:
CHANGES
ALLOWED
CHANGING:
STATE NOT
KNOWN
N/A
CENTER LINE
IS HIGH
IMPEDANCE
11
FN8128.3
June 1, 2006