ISL6115 Datasheet, PDF (11/13 Pages) Intersil Corporation – Power Distribution Controllers

ISL6115, ISL6116, ISL6117, ISL6120
ISL6115EVAL1Z Board
The ISL6115EVAL1Z is default provided as a +12V high
side switch controller with the CR level set at ~1.5A.
See Figure 21 for ISL6115EVAL1Z schematic and Table
4 for BOM. Bias and load connection points are
provided along with test points for each IC pin.
With J1 installed the ISL6115 will be biased from the
+12V supply (V_IN) being switched. Connect the load to
VLOAD+. PWRON pin pulls high internally enabling the
ISL6115 if not driven low via PWRON test point or J2.
With R₃ = 750Ω the CR Vth is set to 15mV and with
the 10mΩ sense resistor (R₁) the ISL6115EVAL1Z has
a nominal CR level of 1.5A. The 0.01µF delay time to
latch-off capacitor results in a nominal 1ms before
latch-off of output after an OC event.
Also included with the ISL6115EVAL1Z board are one
each of the ISL6116, ISL6117 and ISL6120 for
evaluation of those ICs in a high side application.
Remove J1 and provide a separate +12V IC bias supply
via V_BIAS test point.
Reconfiguring the ISL6115EVAL1Z board for a higher
CR level can be done by changing the R_SENSE and/or
R_ISET resistor values as the provided FET is rated for a
much higher current.
ISL6116EVAL1 Board
The ISL6116EVAL1 is default configured as a negative
voltage low side switch controller with a ~2.4A CR
level. See Figure 22 for ISL6116EVAL1 schematic and
Table 4 for BOM and component description. This basic
configuration is capable of controlling both larger
positive or negative potential voltages with minimal
changes.
Bias and load connection points are provided in
addition to test points, TP1 to TP8 for each IC pin. The
terminals, J1 and J4 are for the bus voltage and return,
respectively, with the more negative potential being
connected to J4. With the load between terminals J2
and J3 the board is now configured for evaluation. The
device is enabled through LOGIN, TP9 with a TTL
signal. ISL6116EVAL1 includes a level shifting circuit
with an opto-coupling device for the PWRON input so
that standard TTL logic can be translated to the -V
reference for chip control.
When controlling a positive voltage, PWRON can be
accessed at TP8.
The ISL6116EVAL1 is provided with a high voltage
linear regulator for convenience to provide chip bias
from ±24V to ±350V. This can be removed and
replaced with the zener and resistor bias scheme as
discussed earlier. High voltage regulators and power
discrete devices are no longer available from Intersil
but can be purchased from other semiconductor
manufacturers.
Reconfiguring the ISL6116EVAL1 board for a higher CR
level can be done by changing the R_SENSE and R_ISET
resistor values as the provided FET is 75A rated. If
evaluation at >60V, an alternate FET must be chosen
with an adequate BV_DSS.
VLOAD+
AGND
HI J2 LOAD
J1
C1
+VBUS
J3 LO
Q2
R7
R1
R2
J4
-VBUS
VOUT
R3
R1
U1
R2
C1
VIN
1
8
2 _ISL6115 7
3
U2
6
4
5
C2
J2
PWRON
PGOOD
C_TIM
C3
R4
J1
+12V
V_BIAS
V_BIAS
PWRON
C3
ISL6116
TP8
U1
R
G
1
R6
R11
DD1 ^R5
D2 ^3.3V
LOGIN
TP9
R8
R10
R9
OFF
0V to 5V
OT1 ON
FIGURE 21. ISL6115EVAL1Z HIGH SIDE SWITCH
APPLICATION
FIGURE 22. ISL6116EVAL1 NEGATIVE VOLTAGE LOW
SIDE CONTROLLER
11
FN9100.7
April 29, 2010