ISL54053_0709 Datasheet, PDF (11/11 Pages) Intersil Corporation – Ultra Low ON-Resistance, Low Voltage, Single Supply, SPDT Analog Switch

ISL54053
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
E
AB
PIN 1
D
REFERENCE
2X 0.10 C
2X 0.10 C
TOP VIEW
0.10 C
7X 0.08 C
DETAIL A
A
A1 A3
SIDE VIEW
C
SEATING
PLANE
DETAIL B
1
L1
4X
e
5X
3
L
6
4
BOTTOM VIEW
b 6X
0.10 C A B
0.05 C NOTE 3
0.1x45°
CHAMFER
A1
A3
DETAIL A
DETAIL B PIN 1 LEAD
L6.1.2x1.0A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
MIN NOMINAL MAX
NOTES
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
A3
0.127 REF
-
b
0.15
0.20
0.25
5
D
0.95
1.00
1.05
-
E
1.15
1.20
1.25
-
e
0.40 BSC
-
L
0.30
0.35
0.40
-
L1
0.40
0.45
0.50
-
N
6
2
Ne
3
3
θ
0
-
12
4
NOTES:
Rev. 2 8/06
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Ne refers to the number of terminals on E side.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
1.00
1.40
0.20
0.45
0.30
0.35
0.20
0.40
LAND PATTERN 10
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11
FN6460.2
September 25, 2007