ISL22416 Datasheet, PDF (11/14 Pages) Intersil Corporation – Single Digitally Controlled Potentiometer XDCP

ISL22416
Shutdown Mode
The device can be put in Shutdown mode either by pulling the
SHDN pin to GND or setting the SHDN bit in the ACR register
to 0. The truth table for Shutdown mode is in Table 3.
TABLE 3. SHUTDOWN MODE
SHDN PIN
SHDN BIT
MODE
High
1
Normal operation
Low
1
Shutdown
High
0
Shutdown
Low
0
Shutdown
SPI Serial Interface
The ISL22416 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS must be LOW during
communication with the ISL22416. SCK and CS lines are
controlled by the host or master. The ISL22416 operates
only as a slave device.
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
The first byte sent to the ISL22416 from the SPI host is the
Identification Byte. A valid Identification Byte contains 0101
as the four MSBs, with the following four bits set to 0.
TABLE 4. IDENTIFICATION BYTE FORMAT
0
1
0
1
0
0
0
0
(MSB)
(LSB)
The next byte sent to the ISL22416 contains the instruction
and register pointer information. The four MSBs are the
instruction and two LSBs are register address (see Table 5).
TABLE 5. IDENTIFICATION BYTE FORMAT
7
6
5
4
3
2
1
0
I3
I2
I1
I0
0
0
R1 R0
There are only two valid instruction sets:
1011(binary) - is a Read operation
1100(binary) - is a Write operation
There are only two registers address possible for this DCP. If
the R1, R0 bits are zero, then the read or write is to either the
IVR or the WR register (depends of VOL bit at ACR). If the R1
bit is 1 and R0 bit is 0, then the operation is on the ACR.
Write Operation
A Write operation to the ISL22416 is a three-byte operation.
It requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte followed
by Data Byte is sent to SDI pin. The host terminates the write
operation by pulling the CS pin from LOW to HIGH. For a
write to address 0 (WR), the byte at address 2 (ACR<7>)
determines if the Data Byte is to be written to volatile or both
volatile and non-volatile registers. Refer to “Memory
Description” on page 10 and Figure 16.
The internal non-volatile write cycle starts after rising edge of
CS and takes up to 20ms.
Read Operation
A read operation to the ISL22416 is a three byte operation. It
requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte followed
by “dummy” Data Byte is sent to SDI pin. The SPI host reads
the data from SDO pin on falling edge of SCK. The host
terminates the read operation by pulling the CS pin from
LOW to HIGH (see Figure 17).
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
Applications Information
Communicating with ISL22416
Communication with ISL22416 proceeds using SPI interface
through the ACR (address 10b), IVR (address 00b) and WR
(address 00b) registers.
The wiper of the potentiometer is controlled by the WR
register. Writes and reads can be made directly to this
register to control and monitor the wiper position without any
non-volatile memory changes. This is done by setting MSB
bit at address 10b to 1.
The non-volatile IVR stores the power up value of the wiper.
IVR is accessible when MSB bit at address 10b is set to 0.
Writing a new value to the IVR register will set a new power
up position for the wiper. Also, writing to this register will load
the same value into the WR as the IVR. Reading from the
IVR will not change the WR, if its contents are different.
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FN6227.2
September 9, 2009