HSP43220 Datasheet, PDF (11/21 Pages) Intersil Corporation – Decimating Digital Filter

HSP43220
FIR Output
The 40 most significant bits of the accumulator are latched
into the output register. The lower 3 bits are not brought to
the output. The 40 bits out of the output register are selected
to be output by a pair of multiplexers. This register is clocked
by FIR_CK (see Figure 9).
There are two multiplexers that route 24 of the 40 output bits
from the output register to the output pins. The first
multiplexer selects the output register bits that will be routed
to output pins DATA_OUT16-23 and the second multiplexer
selects the output register bits that will be routed to output
pins DATA_OUT0-15.
The multiplexers are controlled by the control signal F_BYP
and the OUT_SELH pin. F_BYP and OUT_SELH both
control the first multiplexer that selects the upper 8 bits of
the output bus, DATA_OUT16-23. F_BYP controls the
second multiplexer that selects the lower 16 bits of the
output bus, DATA_OUT0-15. The output formatter is shown
in detail in Figure 10.
FIR Control Logic
The DATA_RDY strobe indicates that new data is available on
the output of the FIR. The rising edge of DATA_RDY can be
used to load the output data into an external register or RAM.
Data Format
The DDF maintains 16 bits of accuracy in both the HDF and
FIR filter stages. The data formats and bit weightings are
shown in Figure 11.
PRE-ADDER LOGIC
FROM HDF
16
16 x 512
DATA
RAM
FROM COEFFICIENT
FORMATTER 20
20 x 256
COEFFICIENT
RAM
16
REG ₁₆
F_OAD
PRE-ADDER ₁₇
16
REG ₁₆
F_ESYM
REG
20
REG
REG
17
20
17
FROM CONTROL REGISTERS
F_DRATE
F_TAPS
F_BYP
F_DIS
MULTIPLIER/
ACCUMULATOR
SECTION
F_CLA
17 x 20 BIT MULTIPLIER ARRAY
37
REG
37
43
43-BIT ACCUMULATOR
FIR CONTROL LOGIC
FIR_CK
REG
FIR_CK
DATA_RDY
MUX
43
OUTPUT REG
40
DATA_RDY
F_CLA
OUTPUT
FORMATTER
24
DATA_OUT 0 -23
FIGURE 9. FIR FILTER
11
FN2486.10
October 10, 2008