HIP6004BCB-T Datasheet, PDF (11/15 Pages) Intersil Corporation – Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor

HIP6004B
below). Only the upper MOSFET has switching losses, since
the Schottky rectifier clamps the switching node before the
synchronous rectifier turns on. These equations assume linear
voltage-current transitions and do not adequately model power
loss due the reverse-recovery of the lower MOSFET’s body
diode. The gate-charge losses are dissipated by the HIP6004B
and don't heat the MOSFETs. However, large gate-charge
increases the switching interval, t_SW which increases the upper
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
P_UPPER = Io² x r_DS(ON) x D +
P_LOWER = Io² x r_DS(ON) x (1 - D)
1
2
Io x V_IN x t_SW x F_S
Where: D is the duty cycle = V_OUT / V_IN,
t_SW is the switch ON time, and
F_S is the switching frequency.
Standard-gate MOSFETs are normally recommended for
use with the HIP6004B. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from V_CC. The boot capacitor, C_BOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V_CC
less the boot diode drop (V_D) when the lower MOSFET, Q₂
turns on. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to V_CC.
+12V
D_BOOT
V_CC
HIP6004B
-
+
+ V_D -
+5V OR +12V
BOOT
C_BOOT
Q1
UGATE
PHASE
Q2
LGATE
PGND
GND
NOTE:
V_G-S ≈ V_CC -V_D
D2
NOTE:
V_G-S ≈ V_CC
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
Figure 10 shows the upper gate drive supplied by a direct
connection to V_CC. This option should only be used in
converter systems where the main input voltage is +5V_DC or
less. The peak upper gate-to-source voltage is approximately
V_CC less the input supply. For +5V main power and +12V_DC
for the bias, the gate-to-source voltage of Q₁ is 7V. A logic-
level MOSFET is a good choice for Q₁ and a logic-level
MOSFET can be used for Q₂ if its absolute gate-to-source
voltage rating exceeds the maximum voltage applied to V_CC.
+12V
V_CC
HIP6004B
BOOT
UGATE
PHASE
-
LGATE
+
PGND
GND
+5V OR LESS
Q₁
NOTE:
V_G-S ≈ V_CC -5V
Q₂
D₂
NOTE:
V_G-S ≈ V_CC
FIGURE 10. UPPER GATE DRIVE - DIRECT V_CC DRIVE OPTION
Schottky Selection
Rectifier D₂ is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency will drop
one or two percent as a result. The diode’s rated reverse
breakdown voltage must be greater than the maximum
input voltage.
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