HI5808 Datasheet, PDF(11/12 Page) Intersil Corporation

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HI5808 Datasheet, PDF (11/12 Pages) Intersil Corporation – 12-Bit, 10 MSPS A/D Converter

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HI5808

Dynamic Performance Deï¬nitions

Fast Fourier Transform (FFT) techniques are used to

evaluate the dynamic performance of the HI5808. A low

distortion sine wave is applied to the input, it is coherently

sampled, and the output is stored in RAM. The data is then

transformed into the frequency domain with an FFT and ana-

lyzed to evaluate the dynamic performance of the A/D. The

sine wave input to the part is -0.5dB down from full scale for

all these tests. SNR and SINAD are quoted in dB. The

distortion numbers are quoted in dBc (decibels with respect

to carrier) and DO NOT include any correction factors for

normalizing to full scale.

Signal-to-Noise Ratio (SNR)

SNR is the measured RMS signal to RMS noise at a

speciï¬ed input and sampling frequency. The noise is the

RMS sum of all of the spectral components except the

fundamental and the ï¬rst ï¬ve harmonics.

Signal-to-Noise + Distortion Ratio (SINAD)

SINAD is the measured RMS signal to RMS sum of all

other spectral components below the Nyquist frequency,

fS/2, excluding DC.

Effective Number Of Bits (ENOB)

The effective number of bits (ENOB) is calculated from the

SINAD data by:

ENOB = (SINAD + VCORR-1.76)/6.02,

where: VCORR = 0.5dB.

VCORR adjusts the ENOB for the amount the input is below

full scale.

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the ï¬rst 5 harmonic

components to the RMS value of the fundamental input

signal.

2nd and 3rd Harmonic Distortion

This is the ratio of the RMS value of the applicable

harmonic component to the RMS value of the fundamental

input signal.

Spurious Free Dynamic Range (SFDR)

SFDR is the ratio of the fundamental RMS amplitude to the

RMS amplitude of the next largest spur or spectral compo-

nent in the spectrum below fS/2.

Intermodulation Distortion (IMD)

Nonlinearities in the signal path will tend to generate inter-

modulation products when two tones, f1 and f2, are present

at the inputs. The ratio of the measured signal to the

distortion terms is calculated. The terms included in the

calculation are (f1 + f2), (f1 - f2), (2f1), (2f2), (2f1 + f2),

(2f1 - f2), (f1 + 2f2), (f1 - 2f2). The ADC is tested with each

tone 6dB below full scale.

Transient Response

Transient response is measured by providing a full-scale

transition to the analog input of the ADC and measuring the

number of cycles it takes for the output code to settle within

12-bit accuracy.

Over-Voltage Recovery

Over-voltage Recovery is measured by providing a full-scale

transition to the analog input of the ADC which overdrives

the input by 200mV, and measuring the number of cycles it

takes for the output code to settle within 12-bit accuracy.

Full Power Input Bandwidth (FPBW)

Full power input bandwidth is the analog input frequency at

which the amplitude of the digitally reconstructed output has

decreased 3dB below the amplitude of the input sinewave.

The input sinewave has an amplitude which swings from -fS

to +fS. The bandwidth given is measured at the speciï¬ed

sampling frequency.

Timing Deï¬nitions

Refer to Figure 1, Internal Circuit Timing, and Figure 2,

Input-To-Output Timing, for these deï¬nitions.

Aperture Delay (tAP)

Aperture delay is the time delay between the external

sample command (the falling edge of the clock) and the time

at which the signal is actually sampled. This delay is due to

internal clock path propagation delays.

Aperture Jitter (tAJ)

Aperture Jitter is the RMS variation in the aperture delay due

to variation of internal clock path delays.

Data Hold Time (tH)

Data hold time is the time to where the previous data (N - 1)

is no longer valid.

Data Output Delay Time (tOD)

Data output delay time is the time to where the new data (N)

is valid.

Data Latency (tLAT)

After the analog sample is taken, the digital data is output on

the bus at the third cycle of the clock. This is due to the pipe-

line nature of the converter where the data has to ripple

through the stages. This delay is speciï¬ed as the data

latency. After the data latency time, the data representing

each succeeding sample is output at the following clock

pulse. The digital data lags the analog input sample by 3

clock cycles.

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