ISL95839 Datasheet, PDF (10/36 Pages) Intersil Corporation – Dual 3+1 PWM Controller with Current Monitor for IMVP-7/VR12™ CPUs

ISL95839
Gate Driver Timing Diagram
PWM
UGATE
t_LGFUGR
t_RU
t_FU
1V
LGATE
1V
t_FL
t_RL
t_UGFLGR
Theory of Operation
Multiphase R3™ Modulator
The ISL95839 is a multiphase regulator implementing Intel™
IMVP-7/VR12™ protocol. It has two voltage regulators, VR1 and
VR2, on one chip. VR1 can be programmed for 1-, 2- or 3-phase
operation, and VR2 is 1-phase operation. The following description
is based on VR1, but also applies to VR2 because they are based
on the same architecture.
The ISL95839 uses Intersil patented R3™ (Robust Ripple
Regulator™) modulator. The R3™ modulator combines the best
features of fixed frequency PWM and hysteretic PWM while
eliminating many of their shortcomings. Figure 4 conceptually
shows the multiphase R3™ modulator circuit, and Figure 5 shows
the operation principles.
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C_rm with a current source equal
to g_mV_o, where g_m is a gain factor. C_rm voltage V_crm is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If VR1 is in 3-phase
mode, the master clock signal will be distributed to the three
phases, and the Clock1~3 signals will be 120° out-of-phase. If
VR1 is in 2-phase mode, the master clock signal will be
distributed to Phases 1 and 2, and the Clock1 and Clock2 signals
will be 180° out-of-phase. If VR1 is in 1-phase mode, the master
clock signal will be distributed to Phase 1 only and will be the
Clock1 signal.
Each slave circuit has its own ripple capacitor C_rs, whose voltage
mimics the inductor ripple current. A g_m amplifier converts the
inductor voltage into a current source to charge and discharge
C_rs. The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges C_rs. When C_rs
voltage V_Crs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges C_rs.
Since the controller works with V_crs, which are large-amplitude
and noise-free synthesized signals, it achieves lower phase jitter
than conventional hysteretic mode and fixed PWM mode
controllers. Unlike conventional hysteretic mode converters, the
ISL95839 uses an error amplifier that allows the controller to
maintain a 0.5% output voltage accuracy.
VW
MASTER CLOCK CIRCUIT
MASTER
MASTER ^COMP
CLOCK _Vcrm
CLOCK
Phase
Sequencer
gmVo
Crm
Clock1
Clock2
Clock3
VW
Vcrs1
Crs1
VW
Vcrs2
Crs2
VW
Vcrs3
Crs3
SLAVE CIRCUIT 1
Clock1 S PWM1 ^{Phase1 L1}
Q
R
IL1
gm
SLAVE CIRCUIT 2
Clock2 S PWM2 ^{Phase2 L2}
Q
R
IL2
gm
SLAVE CIRCUIT 3
Clock3 S PWM3 ^{Phase3 L3}
Q
R
IL3
gm
Vo
Co
FIGURE 4. R³â„¢ MODULATOR CIRCUIT
10
FN8315.0
May 9, 2013