ISL8121 Datasheet, PDF (10/26 Pages) Intersil Corporation – 3V to 20V, Two-Phase Buck PWM Controller with Integrated 4A MOSFET Drivers

ISL8121
has a combined ripple frequency twice the frequency of
one of its phases. In addition, the peak-to-peak
amplitude of the combined inductor currents is
proportionately reduced. Increased ripple frequency and
lower ripple amplitude generally translate to lower per-
channel inductance and/or lower total output capacitance
for any given set of performance specification.
C_IN CURRENT
I_L1 + I_L2
I_L2
PWM2
I_L1
PWM1
FIGURE 3. PWM AND INDUCTOR-CURRENT
WAVEFORMS FOR 2-PHASE CONVERTER
Figure 3 illustrates the additive effect on output ripple
frequency. The two channel currents (I_L1 and I_L2),
combine to form the AC ripple current and the DC load
current. The ripple component has two times the ripple
frequency of each individual channel current.
To understand the reduction of ripple current amplitude
in the multi-phase circuit, examine Equation 3, which
represents an individual channel’s peak-to-peak inductor
current.
I_{L, PP =} ⁽_---^V_----^I_--^N_{-----–-L----}^V_-⋅---^O_f--S--^U_---⋅--^T_--V-⁾_---I-^â‹_-N---^V_----^O_----^U_-----^T_-
(EQ. 3)
V_IN and V_OUT are the input and output voltages,
respectively, L is the single-channel inductor value, and
f_S is the switching frequency.
The output capacitors conduct the ripple component of
the inductor current. In the case of multi-phase
converters, the capacitor current is the sum of the ripple
currents from each of the individual channels.
I_PP=
(_---V_{----I--N-----–-----}N_------⋅_----V_{----O-----U----T---})_----⋅_----V_{----O----U-----T-}
L ⋅ f_S ⋅ V_IN
(EQ. 4)
Peak-to-peak ripple current decreases by an amount
proportional to the number of channels. Output-voltage
ripple is a function of capacitance, capacitor equivalent
series resistance (ESR), and inductor ripple current.
Reducing the inductor ripple current allows the designer
to use fewer or less costly output capacitors (should
output high-frequency ripple be an important design
parameter).
Q1 D-S CURRENT
Q3 D-S CURRENT
FIGURE 4. INPUT CAPACITOR CURRENT AND
INDIVIDUAL CHANNEL CURRENTS IN A
2-PHASE CONVERTER
Another benefit of interleaving is the reduction of input
ripple current. Input capacitance is determined in a large
part by the maximum input ripple current. Multi-phase
topologies can improve overall system cost and size by
lowering input ripple current and allowing the designer to
reduce the cost of input capacitance. The example in
Figure 4 illustrates input currents from a two-phase
converter combining to reduce the total input ripple
current.
Figure 28, part of “Input Capacitor Selection” on
page 24, can be used to determine the input-capacitor
RMS current based on load current and duty cycle. The
figure is provided as an aid in determining the optimal
input capacitor solution.
PWM OPERATION
One switching cycle for the ISL8121 is defined as the
time between consecutive PWM pulse terminations (turn-
off of the upper MOSFET on a channel). Each cycle begins
when a switching clock signal commands the upper
MOSFET to go off. The other channel’s upper MOSFET
conduction is terminated 1/2 of a cycle later.
Once a channel’s upper MOSFET is turned off, the lower
MOSFET remains on for a minimum of 1/3 cycle. This
forced off time is required to assure an accurate current
sample. Following the 1/3-cycle forced off time, the
controller enables the upper MOSFET output. Once
enabled, the upper MOSFET output transitions high when
the sawtooth signal crosses the adjusted error-amplifier
output signal, as illustrated in Figure 2. Just prior to the
upper drive turning the MOSFET on, the lower MOSFET
drive turns the freewheeling element off. The upper
MOSFET is kept on until the clock signals the beginning of
the next switching cycle and the PWM pulse is
terminated.
10
FN6352.2
October 27, 2009