ISL6569 Datasheet, PDF (10/22 Pages) Intersil Corporation – Multi-Phase PWM Controller

ISL6569
Current Sensing
During the forced off time following a PWM transition low, the
controller senses channel load current by sampling the
voltage across the lower MOSFET r_DS(ON). A ground-
referenced amplifier, internal to the ISL6569, connects to the
PHASE node through a resistor, R_ISEN. The voltage across
R_ISEN is equivalent to the voltage drop across the r_DS(ON)
of the lower MOSFET while it is conducting. The resulting
current into the ISEN pin is proportional to the channel
current, I_L. The ISEN current is then sampled and held after
sufficient settling time every switching cycle. The sampled
current is used for channel-current balance, load-line
regulation, overcurrent protection, and module current
sharing.
The circuitry shown in Figure 4 represents channel-1 of a
two channel converter. This circuitry is repeated for
channel-2 of the converter. From Figure 4, the following
equation for channel-1 sampled current, I₁, is derived
I₁
=
I_L1
r---_{D----S----(--O----N-----)}
R_ISEN
(EQ. 3)
where I_L1 is half of the total load current.
If r_DS(ON) sensing is not desired, an independent current-
sense resistor in series with the lower MOSFET source can
serve as a sense element.
Channel-Current Balance
The sampled current from both channels, I₁ and I₂, is used
to gauge both overall load current and the relative channel
current carried in each leg of the converter. The individual
sample currents are averaged. The resulting average
current, I_AVG, provides a measure of the total load current
demand on the converter and the appropriate level of
channel current. Using Figures 4 and 5, the average current
is defined as
I_AVG
=
-I-¹-----+-----I--²-
2
I_AVG
=
-I-^O-----^U----^T--
2
r---_{D----S----(--O----N-----)}
R_ISEN
(EQ. 4)
where I_OUT is the total load current.
The average current is then subtracted from the individual
channel sample currents. The resulting error current, I_ER, is
then filtered before it adjusts V_COMP. The modified V_COMP
signal is compared to a sawtooth ramp signal and produces
a pulse width which corrects for any unbalance and drives
the error current toward zero. Figure 5 illustrates Intersil’s
patented current balance method as implemented on one
channel of a multi-phase converter.
V_COMP
+
-
f(jω)
+
-
SAWTOOTH SIGNAL
I_ER
I_{AVG ÷ 2}
Σ
-
+
PWM1
I₂
I₁
FIGURE 5. CHANNEL-1 PWM FUNCTION AND
CURRENT-BALANCE ADJUSTMENT
Two considerations designers face are MOSFET selection
and inductor design. Both are significantly improved when
channel currents track at any load level. The need for
complex drive schemes for multiple MOSFETs, exotic
magnetic materials, and expensive heat sinks is avoided.
Resulting in a cost-effective and easy to implement solution
relative to single-phase conversion. Channel current balance
insures the thermal advantage of multi-phase conversion is
realized. Heat dissipation is spread over multiple channels
and a greater area than single phase approaches.
In some circumstances, it may be necessary to deliberately
design some channel-current unbalance into the system. In
a highly compact design, one channel may be able to cool
more effectively than the other due to nearby air flow or heat
sinking components. The other channel may have more
difficulty cooling with comparatively less air flow and heat
sinking. The hotter channel may also be located close to
other heat-generating components tending to drive it’s
temperature even higher. In these cases, the proper
selection of the current sense resistors (R_ISEN in Figure 4)
introduces channel current unbalance into the system.
Increasing the value of R_ISEN in the cooler channel and
decreasing it in the hotter channel moves both channels into
thermal balance at the expense of current balance.
Voltage Regulation
The output of the error amplifier, V_COMP, is compared to the
sawtooth waveform to modulate the pulse width of the PWM
signals. The PWM signals control the timing of the Intersil
MOSFET drivers and regulate the converter output to the
specified reference voltage. Three distinct inputs to the error
amplifier determine the voltage level of V_COMP. The internal
and external circuitry which control voltage regulation is
illustrated in Figure 6.
10
FN9085.7
December 29, 2004