ISL6292C Datasheet, PDF (10/11 Pages) Intersil Corporation – Li-ion/Li Polymer Battery Charger

ISL6292C
Stability With Large Ceramic Output Capacitors
The ISL6292C partially relies on the ESR (equivalent series
resistance) of the output capacitor for the loop stability.
When the system has a large ceramic capacitor or a number
of ceramic capacitors in parallel, the ESR value can be too
low for a stable operation. A low-value resistor should be
inserted between the sensed feedback (VSEN pin) and the
external large-value ceramic capacitor to improve the
stability, as shown in Figure 9.
In applications that have a sense resistor between the VBAT
pin and the VSEN pin, such as the R₁ shown in Figure 10,
two small resistors can be used to create an equivalent low
value resistor between the VSEN pin and the large capacitor,
to avoid another more expensive low-value sense resistor.
R₂ and R₃ in Figure 10 show how the two resistors are
connected. The equivalent low-value resistance is,
R_eq= _R-----₂--^R---+--³--_R-----₃- ⋅ R₁
(EQ. 7)
The value of (R₂ + R₃) should be significantly larger than
that of the sense resistor R₁ to minimize the accuracy of the
current sensing. The parallel value of R₂ and R₃ should be
significantly smaller than 72kΩ (internal resistive divider
value for setting the charger output voltage) to minimize the
impact on the output voltage. Figure 10 shows two 20Ω
resistor. The sum is 40Ω, much higher than the 150mΩ R₁.
The parallel value is 10Ω, negligible compared to the 72kΩ
resistive divider. Such a selection is a good trade-off to result
in 75mΩ equivalent low-value resistance between the VSEN
pin and the large capacitor.
To INPUT
ISL6292C
VIN
VBAT
C₁
10µF
Ceramic
VSEN
GND
R₁ 75mΩ _{To Battery}
C₂
Large
Ceramic
Capacitor
To INPUT
ISL6292C
VIN
VBAT
R₁ 150mΩ
To Battery
C₁
10µF
Ceramic
VSEN
GND
R₂ 20Ω
R₃ 20Ω
C₂
Large
Ceramic
Capacitor
FIGURE 10. THE CIRCUIT TO GENERATE THE EQUIVALENT
LOW-VALUE RESISTOR
Working with Current-Limited Adapter
The ISL6292C can work with a current-limited adapter to
significantly reduce the thermal dissipation during charging.
Refer to the ISL6292 data sheet, which can be found at
http://www.intersil.com, for more details.
Board Layout Recommendations
The ISL6292C internal thermal foldback function limits the
charge current when the internal temperature reaches
approximately 100°C. In order to maximize the current
capability, it is very important that the exposed pad under the
package is properly soldered to the board and is connected
to other layers through thermal vias. More thermal vias and
more copper attached to the exposed pad usually result in
better thermal performance. On the other hand, the number
of vias is limited by the size of the pad. The 3x3 DFN
package allows 8 vias be placed in two rows. Since the pins
on the 3x3 DFN package are on only two sides, as much top
layer copper as possible should be connected to the
exposed pad to minimize the thermal impedance. Refer to
the ISL6292 evaluation boards for layout examples.
FIGURE 9. INSERTING R₁ TO IMPROVE THE STABILITY OF
APPLICATIONS WITH LARGE CERAMIC
CAPACITOR IS USED AT THE OUTPUT
10
FN9133.2
July 22, 2005