ISL59448 Datasheet, PDF (10/14 Pages) Intersil Corporation – 500MHz Triple 2:1 Gain-of-2, Multiplexing Amplifier

ISL59448
Pin Descriptions
ISL59448
(24 LD QSOP) PIN NAME
8
IN1A
4, 7, 9, 13, 15, 24
NIC
10
IN1B
12
IN1C
5
GNDB
11
GNDC
14
S0
17
OUTC
18
OUTB
16
V-
20
OUTA
19
V+
22
ENABLE
23
LE
21
HIZ
6
IN0C
3
IN0B
1
IN0A
2
GNDA
EQUIVALENT
CIRCUIT
Circuit 1
Circuit 1
Circuit 1
Circuit 4
Circuit 4
Circuit 2
Circuit 3
Circuit 3
Circuit 4
Circuit 3
Circuit 4
Circuit 2
Circuit 2
Circuit 2
Circuit 1
Circuit 1
Circuit 1
Circuit 4
DESCRIPTION
Channel 1 input for output amplifier "A"
Not Internally Connected; it is recommended these pins be tied to ground to minimize
crosstalk.
Channel 1 input for output amplifier "B"
Channel 1 input for output amplifier "C"
Ground pin for output amplifier “B”
Ground pin for output amplifier “C”
Channel selection pin. LSB (binary logic code)
Output of amplifier “C”
Output of amplifier “B”
Negative power supply
Output of amplifier “A”
Positive power supply
Device enable (active low) w/Internal pull-down resistor. A logic High puts device into
power-down mode with the only logic circuitry active. All logic states are preserved post
power-down. This state is not recommended for logic control where more than one MUX-
amp share the same video output line.
Device latch enable on the ISL59424. A logic high on LE will latch the last (S0, S1) logic
state. HIZ and ENABLE functions are not latched with the LE pin.
Output disable (active high) w/internal pull-down resistor. A logic high, puts the outputs in
a high impedance state. Use this state to control logic when more than one MUX-amp
share the same video output line.
Channel 0 for output amplifier "C"
Channel 0 for output amplifier "B"
Channel 0 for output amplifier "A"
Ground pin for output amplifier “A”
10
FN6160.2
March 29, 2006