ISL5857_15 Datasheet, PDF (10/14 Pages) Intersil Corporation – 12-bit, +3.3V, 260+MSPS, High Speed D/A Converter

ISL5857
Ground Planes
Separate digital and analog ground planes should be used. All
of the digital functions of the device and their corresponding
components should be located over the digital ground plane
and terminated to the digital ground plane. The same is true
for the analog components and the analog ground plane.
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AV_DD and DV_DD. Also, the layout should be designed
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for DV_DD
and to the analog ground for AV_DD. Additional filtering of the
power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal value
of +1.23V with a ±40ppm/°C drift coefficient over the full
temperature range of the converter. It is recommended that a
0.1µF capacitor be placed as close as possible to the REFIO
pin, connected to the analog ground. The REFLO pin (16)
selects the reference. The internal reference can be selected if
pin 16 is tied low (ground). If an external reference is desired,
then pin 16 should be tied high (the analog supply voltage) and
the external reference driven into REFIO, pin 17. The full scale
output current of the converter is a function of the voltage
reference used and the value of R_SET. I_OUT should be within
the 2mA to 20mA range, though operation below 2mA is
possible with performance degradation.
If the internal reference is used, V_FSADJ will equal
approximately 1.2V (pin 18). If an external reference is used,
V_FSADJ will equal the external reference. The calculation for
I_OUT (Full Scale) is:
I_OUT(Full Scale) = (V_FSADJ/R_SET) x 32
If the full scale output current is set to 20mA by using the
internal voltage reference (1.2V) and a 1.91kΩ R_SET resistor,
then the input coding to output current will resemble the
following:
TABLE 1. INPUT CODING vs OUTPUT CURRENT WITH INTERNAL
REFERENCE AND RSET = 1.91kΩ
INPUT CODE (D11-D0)
IOUTA (mA)
IOUTB (mA)
11 11111 11111
20
0
10 00000 00000
10
10
00 00000 00000
0
20
Analog Output
IOUTA and IOUTB are complementary current outputs. The sum
of the two currents is always equal to the full scale output
current minus one LSB. If single-ended use is desired, a load
resistor can be used to convert the output current to a voltage.
It is recommended that the unused output be either grounded
or equally terminated. The voltage developed at the output
must not violate the output voltage compliance range of -1.0V
to 1.25V. R_OUT (the impedance loading each current output)
should be chosen so that the desired output voltage is
produced in conjunction with the output full scale current. If a
known line impedance is to be driven, then the output load
resistor should be chosen to match this impedance. The output
voltage equation is:
V_OUT = I_OUT x R_OUT.
The most effective method for reducing the power
consumption is to reduce the analog output current, which
dominates the supply current. The maximum recommended
output current is 20mA.
Differential Output
IOUTA and IOUTB can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. With
R_DIFF = 50Ωand R_LOAD = 50Ω, the circuit in Figure 15 will
provide a 500mV signal at the output of the transformer if the
full scale output current of the DAC is set to 20mA (used for
the electrical specifications table). Values of R_DIFF = 100Ωand
R_LOAD = 50Ω were used for the typical performance curves.
The center tap in Figure 15 must be grounded.
In the circuit in Figure 16, the user is left with the option to
ground or float the center tap. The DC voltage that will exist at
either IOUTA or IOUTB if the center tap is floating is IOUT_DC x
(R_A//R_B) V because R_DIFF is DC shorted by the transformer. If
the center tap is grounded, the DC voltage is 0V.
Recommended values for the circuit in Figure 16 are
R_A = R_B = 50Ω, R_DIFF = 100Ω, assuming R_LOAD = 50Ω. The
performance of Figures 15 and 16 is basically the same,
however leaving the center tap of Figure 16 floating allows the
circuit to find a more balanced virtual ground, theoretically
improving the even order harmonic rejection, but likely
reducing the signal swing available due to the output voltage
compliance range limitations.
Submit Document Feedback ₁₀
FN6079.3
October 7, 2015