ISL29044A_14 Datasheet, PDF (10/19 Pages) Intersil Corporation – Low Power Ambient Light and Proximity Sensor with Internal IR-LED and Digital Output

ISL29044A
Device Addressing
Following a START condition, the master must output a Device
Address byte. The 7 MSBs of the Device Address byte are known as
the device identifier. The device identifier bits of ISL29044A are
internally hard-wired as “1000100”. The LSB of the Device Address
byte is defined as read or write (R/W) bit. When this R/W bit is a
“1”, a read operation is selected and when “0”, a write operation is
selected (refer to Figure 18). The master generates a START
condition followed by a Device Address byte 1000100x (x as R/W)
and the ISL29044A compares it with the internal device identifier.
Upon a correct comparison, the device outputs an acknowledge
(LOW) on the SDA line (refer to Figure 17).
1
0
0
0
1
0
0
R/W
DEVICE
ADDRESS BYTE
A7
A6
A5
A4
A3
A2
A1
A0
REGISTER
ADDRESS BYTE
Read Operation
The ISL29044A has two basic read operations: Byte Read and
Burst Read.
BYTE READ
Byte read operations allow the master to access any register
location in the ISL29044A. The Byte read operation is a two step
process. The master issues the START condition and the Device
Address byte with the R/W bit set to “0”, receives an
acknowledge, then issues the Register Address byte. After
acknowledging receipt of the register address byte, the master
immediately issues another START condition and the Device
Address byte with the R/W bit set to “1”. This is followed by an
acknowledge from the device and then by the 8-bit data word.
The master terminates the read operation by not responding with
an acknowledge and then issuing a stop condition (refer to
Figure 20).
D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE
FIGURE 18. DEVICE ADDDRESS, REGISTER ADDRESS, and DATA
BYTE
Write Operation
BYTE WRITE
In a byte write operation, the ISL29044A requires the Device
Address byte, Register Address byte, and the Data byte. The
master starts the communication with a START condition. Upon
receipt of the Device Address byte, Register Address byte, and
the Data byte, the ISL29044A responds with an acknowledge
(ACK). Following the ISL29044A data acknowledge response, the
master terminates the transfer by generating a STOP condition.
The ISL29044A then begins an internal write cycle of the data to
the volatile memory. During the internal write cycle, the device
inputs are disabled and the SDA line is in a high impedance state,
so the device will not respond to any requests from the master
(refer to Figure 19).
SIGNAL FROM
MASTER DEVICE
SIGNAL AT SDA
SIGNALS FROM
SLAVE DEVICE
S
T
A
R
DEVICE ADDRESS
BYTE
T
10001000
ADDRESS BYTE
S
DATA BYTE
T
O
P
A
A
A
C
C
C
K
K
K
FIGURE 19. BYTE WRITE SEQUENCE
BURST WRITE
The ISL29044A has a burst write operation, which allows the
master to write multiple consecutive bytes from a specific
address location. It is initiated in the same manner as the byte
write operation, but instead of terminating the write cycle after
the first Data byte is transferred, the master can write to the
whole register array. After the receipt of each byte, the
ISL29044A responds with an acknowledge, and the address is
internally incremented by one. The address pointer remains at
the last address byte written. When the counter reaches the end
of the register address list, it “rolls over” and goes back to the
first Register Address.
10
FN8419.1
April 19, 2013