ISL12008 Datasheet, PDF (10/19 Pages) Intersil Corporation – I2C Real Time Clock with Battery Backup

ISL12008
Real Time Clock Registers
TABLE 1. REGISTER MEMORY MAP
BIT
REG
ADDR. SECTION NAME
7
6
5
4
3
2
00h
RTC
SC
ST
SC22
SC21
SC20
SC13
SC12
01h
MN
OF
MN22 MN21 MN20 MN13 MN12
02h
HR
CEB
CB
HR21
HR20
HR13
HR12
03h
DW
0
0
0
0
0
DW12
04h
DT
0
0
DT21
DT20
DT13
DT12
05h
MO
0
0
0
MO20 MO13 MO12
06h
YR
YR23
YR22
YR21
YR20
YR13
YR12
07h Control DTR
OUT
FT
DTR5 DTR4 DTR3 DTR2
08h
INT
0
ALME LPMODE
0
0
0
09h
OF
OF
0
0
0
0
0
0Ah
ATR BMATR1 BMATR0 ATR5
ATR4
ATR3
ATR2
0Bh Status
SR
ARST XSTOP RESEAL
0
0
ALM
0Ch Alarm0 SCA ESCA ASC22 ASC21 ASC20 ASC13 ASC12
0Dh
MNA EMNA AMN22 AMN21 AMN20 AMN13 AMN12
0Eh
HRA EHRA
0
AHR21 AHR20 AHR13 AHR12
0Fh
DTA EDTA
0
ADT21 ADT20 ADT13 ADT12
10h
MOA EMOA
0
0
AMO20 AMO13 AMO12
11h
DWA EDWA
0
0
0
0
ADW12
1Fh
(Read-
Only)
RTC
SS
SS23
SS22
SS21
SS20
SS13
SS12
NOTE: 0 = must be set to‘0’
1
SC11
MN11
HR11
DW11
DT11
MO11
YR11
DTR1
0
0
ATR1
BAT
ASC11
AMN11
AHR11
ADT11
AMO11
ADW11
SS11
REG
RTC
0
RANGE DEFAULT
SC10 0 to 59
00h
MN10 0 to 59
80h
HR10 0 to 23
00h
DW10 1 to 7
00h
DT10 1 to 31
00h
MO10 1 to 12
00h
YR10 0 to 99
00h
DTR0
N/A
80h
0
N/A
00h
0
N/A
80h
ATR0
N/A
00h
RTCF
N/A
03h
ASC10 00 to 59 00h
AMN10 00 to 59 00h
AHR10 0 to 23
00h
ADT10 1 to 31
00h
AMO10 1 to 12
00h
ADW10 1 to 7
00h
SS10 0 to 99
00h
Addresses [00h to 06h, and 1Fh]
RTC REGISTERS (SC, MN, HR, DW, DT, MO, YR, SS)
These registers depict BCD representations of the time. As
such, SC (Seconds, address 00h) and MN (Minutes,
address 01h) range from 0 to 59, HR (Hour, address 02h) is
in 24-hour mode with a range from 0 to 23, DW (Day of the
Week, address 03h) is 1 to 7, DT (Date, address 04h) is 1 to
31, MO (Month, address 05h) is 1 to 12, YR (Year, address
06h) is 0 to 99, and SS (Sub-Seconds/Hundredths of
Seconds, address 1Fh) is 0 to 99. The default for all the time
keeping bits are set to “0” at power up.
Bit D7 of SC register contain the crystal enable/disable bit
(ST). Setting ST to “1” will disable the crystal from oscillating
and stop the counting in RTC register. When the ST bit is set
to “1”, it will casue the OF bit to set to “1” due to no crystal
oscillation on the X1 pin. The ST bit is set to “0” on power-up
for normal operation.
Bit D7 of MN register contain the Oscillator Fail Indicator bit
(OF). This bit is set to a “1” when the X1 pin has no
oscillation. This bit can be reset when the X1 has crystal
oscillation and a write to “0”. This bit can only be written as
“0” and not as a “1”. The OF bit is set to “1” at power-up from
a complete power down (V_DD and V_BAT are removed).
Address 9, bit 7 is also used as the OF bit for DS1340
compatibility, and the two OF bits are interchangable.
Bits D6 and D7 of HR register (century/hours register)
contain the century enable bit (CEB) and the century bit
(CB). Setting CEB to a '1' will cause CB to toggle, either from
'0' to '1' or from '1' to '0' at the turn of the century (depending
upon its initial state). If CEB is set to a '0', CB will not toggle.
The DW register provides a Day of the Week status and uses
three bits DW2 to DW0 to represent the seven days of the
week. The counter advances in the cycle 1-2-3-4-5-6-7-1-2-
… The assignment of a numerical value to a specific day of
the week is arbitrary and may be decided by the system
software designer.
10
FN6690.1
September 26, 2008