ICM7226A_01 Datasheet, PDF (10/19 Pages) Intersil Corporation – 8-Digit, Multi-Function, Frequency Counter/Timer

ICM7226A, ICM7226B
RST IN Input
The RST IN is provided to reset the Main Counter, stop any
measurement in progress, and enable the display latches,
resulting in the all zero display. It is suggested to have a
capacitor at this input to V_SS to prevent any hangup problem
on power up. See application circuits.
EXT RANGE Input
This input is provided to select ranges other than those
provided in the chip. In any mode of measurement the duration
of measurement is determined by the EXT RANGE if this input
is enabled. This input is sampled at 10ms intervals by the
100Hz reference derived from the timebase. Figure 12 shows
the relationship between this input, 100Hz reference signal and
MEAS IN PROGRESS. EXT RANGE can change state
anywhere during the period of 100Hz reference by will be
sampled at the trailing edge of the period to start or stop
measurement.
REFERENCE
COUNTER
CLOCK
MEAS
t_r
IN PROGRESS
EXT RANGE
INPUT
FIGURE 12. EXTERNAL RANGE INPUT TO END OF
MEASUREMENT IN PROGRESS
This input should not be used for short arbitrary ranges
(because of its sampling period), it is provided for very long
gating purposes. A way of using the ICM7226 for a short
arbitrary range is to feed the gating signal into the INPUT B
and run the device in the Frequency Ratio mode. Note that
the gating period will be from one positive edge until the next
positive edge of INPUT B (0.01s/1 cycle range).
MEAS IN PROGRESS, STORE, RST OUT Outputs
These outputs are provided for external system interfacing.
MEAS IN PROGRESS stays low during measurements and
goes high for intervals between measurements. Figure 13
shows the relationship between these outputs for intervals
between measurements. All these outputs can drive a low
power Schottky TTL. The MEAS IN PROGRESS can drive
one ECL load if the ECL device is powered from the same
power supply as the ICM7226.
MEAS
IN PROGRESS
STORE
RESET OUT
30ms TO
40ms
190ms TO 200ms
40ms
60ms
40ms
FIGURE 13. RESET OUT, STORE AND MEASUREMENT IN
PROGRESS OUTPUTS BETWEEN MEASUREMENTS
BCD Outputs
The BCD representation of each display digit is available at
the BCD outputs in a multiplexed fashion. See Table 3 for dig-
its truth table. The BCD output of each digit is available when
its corresponding digit output is activated. Note that the digit
outputs are multiplexed from D8 (MSD) to D1 (LSD). The pos-
itive going (ICM7226A, common anode) or the negative going
(ICM7226B, common cathode) digit drive signals lag the BCD
data by 2µs to 6µs. This starting edge of each digit drive sig-
nal should be used to externally latch the BCD data. Each
BCD output drives one low power Schottky TTL load. Leading
zero blanking has no effect on the BCD outputs.
TABLE 3. TRUTH TABLE BCD OUTPUTS
NUMBER
0
1
2
3
4
5
6
7
8
9
BCD 8
PIN 7
0
0
0
0
0
0
0
0
1
1
BCD 4
PIN 6
0
0
0
0
1
1
1
1
0
0
BCD 2
PIN 17
0
0
1
1
0
0
1
1
0
0
BCD 1
PIN 18
0
1
0
1
0
1
0
1
0
1
BUF OSC OUT Output
The BUFFered OSCillator OUTput is provided for use of the
on-board oscillator signal, without loading the oscillator itself.
This output can drive one low power Schottky TTL load. Care
should be taken to minimize capacitive loading on this pin.
Decimal Point Position
Table 4 shows the decimal point position for different modes
of lCM7226 operation. Note that the digit 1 is the least signif-
icant digit. Table is given for 10MHz timebase frequency.
RANGE
0.01s/1 Cycle
0.1s/10 Cycle
1s/100 Cycle
10s/1K Cycle
External
FREQUENCY
D2
D3
D4
D5
N/A
TABLE 4. DECIMAL POINT POSITIONS
PERIOD
FREQUENCY
RATIO
TIME
INTERVAL
D2
D1
D2
D3
D2
D3
D4
D3
D4
D5
D4
D5
N/A
N/A
N/A
UNIT
COUNTER
D1
D1
D1
D1
N/A
OSCILLATOR
FREQUENCY
D2
D3
D4
D5
N/A
10